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Fixed double->single speed switch causing misaligned CPU timing

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This commit is contained in:
Lior Halphon 2021-06-26 13:54:18 +03:00
parent 94add1d172
commit 278224299f
1 changed files with 1 additions and 1 deletions
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2
Core/sm83_cpu.c
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@ -373,7 +373,7 @@ static void leave_stop_mode(GB_gameboy_t *gb)
for (unsigned i = 0x1FFF; i--;) {
GB_advance_cycles(gb, 0x10);
}
GB_advance_cycles(gb, gb->cgb_double_speed? 0x10 : 0xF);
GB_advance_cycles(gb, gb->cgb_double_speed? 0x10 : 0xC);
GB_write_memory(gb, 0xFF00 + GB_IO_DIV, 0);
}