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Fixed channel 3 counter behavior, verified with new tests. The DIV register ticks the APU at 512Hz.

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This commit is contained in:
Lior Halphon 2017-07-22 19:51:11 +03:00
parent a19ee1e5e0
commit 2936f7fa57
2 changed files with 3 additions and 3 deletions
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2
Core/apu.c
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@ -283,7 +283,7 @@ void GB_apu_write(GB_gameboy_t *gb, uint8_t reg, uint8_t value)
}
}
gb->apu.is_active[GB_WAVE] = true;
gb->apu.wave_channel.pulse_length = ~gb->io_registers[GB_IO_NR31];
gb->apu.wave_channel.pulse_length = (~gb->io_registers[GB_IO_NR31]) * 2;
gb->apu.wave_channel.sample_countdown = gb->apu.wave_channel.sample_length + 3;
gb->apu.wave_channel.current_sample_index = 0;
/* Note that we don't change the sample just yet! This was verified on hardware. */

2
Core/apu.h
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@ -11,7 +11,7 @@
#define CH_STEP (MAX_CH_AMP/0xF/7)
#endif
/* Lengths are in either DIV ticks (256Hz, triggered by the DIV register) or
/* Lengths are in either DIV ticks (512Hz, triggered by the DIV register) or
APU ticks (2MHz, triggered by an internal APU clock) */
typedef struct