From 5565c2540b329f95f4fd389954256d7bc97056b0 Mon Sep 17 00:00:00 2001 From: Lior Halphon Date: Sat, 6 Nov 2021 13:34:34 +0200 Subject: [PATCH] Register name and info update --- Core/gb.h | 16 ++++++---------- Core/memory.c | 16 ++++++++-------- Misc/registers.sym | 11 +++++------ 3 files changed, 19 insertions(+), 24 deletions(-) diff --git a/Core/gb.h b/Core/gb.h index 636d98e..a23922a 100644 --- a/Core/gb.h +++ b/Core/gb.h @@ -224,10 +224,7 @@ enum { GB_IO_OBP1 = 0x49, // Object Palette 1 Data (R/W) - Non CGB Mode Only GB_IO_WY = 0x4a, // Window Y Position (R/W) GB_IO_WX = 0x4b, // Window X Position minus 7 (R/W) - // Has some undocumented compatibility flags written at boot. - // Unfortunately it is not readable or writable after boot has finished, so research of this - // register is quite limited. The value written to this register, however, can be controlled - // in some cases. + // Controls DMG mode and PGB mode GB_IO_KEY0 = 0x4c, /* General CGB features */ @@ -260,13 +257,12 @@ enum { /* Missing */ GB_IO_SVBK = 0x70, // CGB Mode Only - WRAM Bank - GB_IO_UNKNOWN2 = 0x72, // (00h) - Bit 0-7 (Read/Write) - GB_IO_UNKNOWN3 = 0x73, // (00h) - Bit 0-7 (Read/Write) - GB_IO_UNKNOWN4 = 0x74, // (00h) - Bit 0-7 (Read/Write) - CGB Mode Only + GB_IO_PSWX = 0x72, // X position of the palette switching window + GB_IO_PSWY = 0x73, // Y position of the palette switching window + GB_IO_PSW = 0x74, // Key combo to trigger the palette switching window GB_IO_UNKNOWN5 = 0x75, // (8Fh) - Bit 4-6 (Read/Write) - GB_IO_PCM_12 = 0x76, // Channels 1 and 2 amplitudes - GB_IO_PCM_34 = 0x77, // Channels 3 and 4 amplitudes - GB_IO_UNKNOWN8 = 0x7F, // Unknown, write only + GB_IO_PCM12 = 0x76, // Channels 1 and 2 amplitudes + GB_IO_PCM34 = 0x77, // Channels 3 and 4 amplitudes }; typedef enum { diff --git a/Core/memory.c b/Core/memory.c index c221352..bcfff64 100644 --- a/Core/memory.c +++ b/Core/memory.c @@ -539,11 +539,11 @@ static uint8_t read_high_memory(GB_gameboy_t *gb, uint16_t addr) } return gb->io_registers[GB_IO_OPRI] | 0xFE; - case GB_IO_PCM_12: + case GB_IO_PCM12: if (!GB_is_cgb(gb)) return 0xFF; return ((gb->apu.is_active[GB_SQUARE_2] ? (gb->apu.samples[GB_SQUARE_2] << 4) : 0) | (gb->apu.is_active[GB_SQUARE_1] ? (gb->apu.samples[GB_SQUARE_1]) : 0)) & (gb->model <= GB_MODEL_CGB_C? gb->apu.pcm_mask[0] : 0xFF); - case GB_IO_PCM_34: + case GB_IO_PCM34: if (!GB_is_cgb(gb)) return 0xFF; return ((gb->apu.is_active[GB_NOISE] ? (gb->apu.samples[GB_NOISE] << 4) : 0) | (gb->apu.is_active[GB_WAVE] ? (gb->apu.samples[GB_WAVE]) : 0)) & (gb->model <= GB_MODEL_CGB_C? gb->apu.pcm_mask[1] : 0xFF); @@ -626,10 +626,10 @@ static uint8_t read_high_memory(GB_gameboy_t *gb, uint16_t addr) } return ret; } - case GB_IO_UNKNOWN2: - case GB_IO_UNKNOWN3: + case GB_IO_PSWX: + case GB_IO_PSWY: return GB_is_cgb(gb)? gb->io_registers[addr & 0xFF] : 0xFF; - case GB_IO_UNKNOWN4: + case GB_IO_PSW: return gb->cgb_mode? gb->io_registers[addr & 0xFF] : 0xFF; case GB_IO_UNKNOWN5: return GB_is_cgb(gb)? gb->io_registers[addr & 0xFF] | 0x8F : 0xFF; @@ -1077,9 +1077,9 @@ static void write_high_memory(GB_gameboy_t *gb, uint16_t addr, uint8_t value) case GB_IO_OBP0: case GB_IO_OBP1: case GB_IO_SB: - case GB_IO_UNKNOWN2: - case GB_IO_UNKNOWN3: - case GB_IO_UNKNOWN4: + case GB_IO_PSWX: + case GB_IO_PSWY: + case GB_IO_PSW: case GB_IO_UNKNOWN5: gb->io_registers[addr & 0xFF] = value; return; diff --git a/Misc/registers.sym b/Misc/registers.sym index 3b31b74..affe663 100644 --- a/Misc/registers.sym +++ b/Misc/registers.sym @@ -57,11 +57,10 @@ 00:FF6B IO_OBPD 00:FF6C IO_OPRI 00:FF70 IO_SVBK -00:FF72 IO_UNKNOWN2 -00:FF73 IO_UNKNOWN3 -00:FF74 IO_UNKNOWN4 +00:FF72 IO_PSWX +00:FF73 IO_PSWY +00:FF74 IO_PSW 00:FF75 IO_UNKNOWN5 -00:FF76 IO_PCM_12 -00:FF77 IO_PCM_34 -00:FF7F IO_UNKNOWN8 +00:FF76 IO_PCM12 +00:FF77 IO_PCM34 00:FFFF IO_IE