Fixed sources-dmgABCXmgbS
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@ -476,7 +476,6 @@ void GB_reset(GB_gameboy_t *gb)
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gb->is_cgb = true;
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gb->cgb_mode = true;
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gb->io_registers[GB_IO_OBP0] = gb->io_registers[GB_IO_OBP1] = 0x00;
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}
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else {
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gb->ram_size = 0x2000;
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@ -494,8 +493,10 @@ void GB_reset(GB_gameboy_t *gb)
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gb->sprite_palettes_rgb[7] = gb->sprite_palettes_rgb[3] = gb->background_palettes_rgb[3] =
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gb->rgb_encode_callback(gb, 0, 0, 0);
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}
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gb->io_registers[GB_IO_OBP0] = gb->io_registers[GB_IO_OBP1] = 0xFF;
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}
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/* These are not deterministic, but 00 (CGB) and FF (DMG) are the most common initial values by far */
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gb->io_registers[GB_IO_DMA] = gb->io_registers[GB_IO_OBP0] = gb->io_registers[GB_IO_OBP1] = gb->is_cgb? 0x00 : 0xFF;
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/* The serial interrupt always occur on the 0xF8th cycle of every 0x100 cycle since boot. */
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gb->serial_cycles = 0x100 - 0xF8;
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gb->io_registers[GB_IO_SC] = 0x7E;
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@ -31,7 +31,7 @@ static GB_bus_t bus_for_addr(GB_gameboy_t *gb, uint16_t addr)
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static bool is_addr_in_dma_use(GB_gameboy_t *gb, uint16_t addr)
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{
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if (!gb->dma_steps_left || (gb->dma_cycles < 0 && !gb->is_dma_restarting)) return false;
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if (!gb->dma_steps_left || (gb->dma_cycles < 0 && !gb->is_dma_restarting) || addr >= 0xFE00) return false;
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return bus_for_addr(gb, addr) == bus_for_addr(gb, gb->dma_current_src);
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}
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@ -174,6 +174,7 @@ static uint8_t read_high_memory(GB_gameboy_t *gb, uint16_t addr)
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case GB_IO_WX:
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case GB_IO_SC:
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case GB_IO_SB:
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case GB_IO_DMA:
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return gb->io_registers[addr & 0xFF];
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case GB_IO_TIMA:
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if (gb->tima_reload_state == GB_TIMA_RELOADING) {
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@ -232,9 +233,6 @@ static uint8_t read_high_memory(GB_gameboy_t *gb, uint16_t addr)
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}
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return ret;
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}
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case GB_IO_DMA:
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/* Todo: is this documented? */
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return gb->is_cgb? 0x00 : 0xFF;
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case GB_IO_UNKNOWN2:
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case GB_IO_UNKNOWN3:
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return gb->is_cgb? gb->io_registers[addr & 0xFF] : 0xFF;
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@ -509,21 +507,18 @@ static void write_high_memory(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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return;
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case GB_IO_DMA:
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if (value <= 0xE0) {
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if (gb->dma_steps_left) {
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/* This is not correct emulation, since we're not really delaying the second DMA.
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One write that should have happened in the first DMA will not happen. However,
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since that byte will be overwritten by the second DMA before it can actually be
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read, it doesn't actually matter. */
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gb->is_dma_restarting = true;
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}
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gb->dma_cycles = -7;
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gb->dma_current_dest = 0;
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gb->dma_current_src = value << 8;
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gb->dma_steps_left = 0xa0;
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if (gb->dma_steps_left) {
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/* This is not correct emulation, since we're not really delaying the second DMA.
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One write that should have happened in the first DMA will not happen. However,
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since that byte will be overwritten by the second DMA before it can actually be
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read, it doesn't actually matter. */
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gb->is_dma_restarting = true;
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}
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/* else { what? } */
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gb->dma_cycles = -7;
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gb->dma_current_dest = 0;
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gb->dma_current_src = value << 8;
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gb->dma_steps_left = 0xa0;
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gb->io_registers[GB_IO_DMA] = value;
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return;
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case GB_IO_SVBK:
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if (!gb->cgb_mode) {
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@ -701,7 +696,14 @@ void GB_dma_run(GB_gameboy_t *gb)
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/* Todo: measure this value */
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gb->dma_cycles -= 4;
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gb->dma_steps_left--;
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gb->oam[gb->dma_current_dest++] = GB_read_memory(gb, gb->dma_current_src);
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if (gb->dma_current_src < 0xe000) {
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gb->oam[gb->dma_current_dest++] = GB_read_memory(gb, gb->dma_current_src);
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}
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else {
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/* Todo: Not correct on the CGB */
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gb->oam[gb->dma_current_dest++] = GB_read_memory(gb, gb->dma_current_src & ~0x2000);
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}
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/* dma_current_src must be the correct value during GB_read_memory */
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gb->dma_current_src++;
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if (!gb->dma_steps_left) {
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