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Fixed sources-dmgABCXmgbS

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This commit is contained in:
Lior Halphon 2018-03-22 20:09:01 +02:00
parent 6176befecb
commit 577e23925b
2 changed files with 24 additions and 21 deletions
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5
Core/gb.c
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@ -476,7 +476,6 @@ void GB_reset(GB_gameboy_t *gb)
gb->is_cgb = true; gb->is_cgb = true;
gb->cgb_mode = true; gb->cgb_mode = true;
gb->io_registers[GB_IO_OBP0] = gb->io_registers[GB_IO_OBP1] = 0x00;
} }
else { else {
gb->ram_size = 0x2000; gb->ram_size = 0x2000;
@ -494,8 +493,10 @@ void GB_reset(GB_gameboy_t *gb)
gb->sprite_palettes_rgb[7] = gb->sprite_palettes_rgb[3] = gb->background_palettes_rgb[3] = gb->sprite_palettes_rgb[7] = gb->sprite_palettes_rgb[3] = gb->background_palettes_rgb[3] =
gb->rgb_encode_callback(gb, 0, 0, 0); gb->rgb_encode_callback(gb, 0, 0, 0);
} }
gb->io_registers[GB_IO_OBP0] = gb->io_registers[GB_IO_OBP1] = 0xFF;
} }
/* These are not deterministic, but 00 (CGB) and FF (DMG) are the most common initial values by far */
gb->io_registers[GB_IO_DMA] = gb->io_registers[GB_IO_OBP0] = gb->io_registers[GB_IO_OBP1] = gb->is_cgb? 0x00 : 0xFF;
/* The serial interrupt always occur on the 0xF8th cycle of every 0x100 cycle since boot. */ /* The serial interrupt always occur on the 0xF8th cycle of every 0x100 cycle since boot. */
gb->serial_cycles = 0x100 - 0xF8; gb->serial_cycles = 0x100 - 0xF8;
gb->io_registers[GB_IO_SC] = 0x7E; gb->io_registers[GB_IO_SC] = 0x7E;

40
Core/memory.c
View File

@ -31,7 +31,7 @@ static GB_bus_t bus_for_addr(GB_gameboy_t *gb, uint16_t addr)
static bool is_addr_in_dma_use(GB_gameboy_t *gb, uint16_t addr) static bool is_addr_in_dma_use(GB_gameboy_t *gb, uint16_t addr)
{ {
if (!gb->dma_steps_left || (gb->dma_cycles < 0 && !gb->is_dma_restarting)) return false; if (!gb->dma_steps_left || (gb->dma_cycles < 0 && !gb->is_dma_restarting) || addr >= 0xFE00) return false;
return bus_for_addr(gb, addr) == bus_for_addr(gb, gb->dma_current_src); return bus_for_addr(gb, addr) == bus_for_addr(gb, gb->dma_current_src);
} }
@ -174,6 +174,7 @@ static uint8_t read_high_memory(GB_gameboy_t *gb, uint16_t addr)
case GB_IO_WX: case GB_IO_WX:
case GB_IO_SC: case GB_IO_SC:
case GB_IO_SB: case GB_IO_SB:
case GB_IO_DMA:
return gb->io_registers[addr & 0xFF]; return gb->io_registers[addr & 0xFF];
case GB_IO_TIMA: case GB_IO_TIMA:
if (gb->tima_reload_state == GB_TIMA_RELOADING) { if (gb->tima_reload_state == GB_TIMA_RELOADING) {
@ -232,9 +233,6 @@ static uint8_t read_high_memory(GB_gameboy_t *gb, uint16_t addr)
} }
return ret; return ret;
} }
case GB_IO_DMA:
/* Todo: is this documented? */
return gb->is_cgb? 0x00 : 0xFF;
case GB_IO_UNKNOWN2: case GB_IO_UNKNOWN2:
case GB_IO_UNKNOWN3: case GB_IO_UNKNOWN3:
return gb->is_cgb? gb->io_registers[addr & 0xFF] : 0xFF; return gb->is_cgb? gb->io_registers[addr & 0xFF] : 0xFF;
@ -509,21 +507,18 @@ static void write_high_memory(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
return; return;
case GB_IO_DMA: case GB_IO_DMA:
if (value <= 0xE0) { if (gb->dma_steps_left) {
if (gb->dma_steps_left) { /* This is not correct emulation, since we're not really delaying the second DMA.
/* This is not correct emulation, since we're not really delaying the second DMA. One write that should have happened in the first DMA will not happen. However,
One write that should have happened in the first DMA will not happen. However, since that byte will be overwritten by the second DMA before it can actually be
since that byte will be overwritten by the second DMA before it can actually be read, it doesn't actually matter. */
read, it doesn't actually matter. */ gb->is_dma_restarting = true;
gb->is_dma_restarting = true;
}
gb->dma_cycles = -7;
gb->dma_current_dest = 0;
gb->dma_current_src = value << 8;
gb->dma_steps_left = 0xa0;
} }
/* else { what? } */ gb->dma_cycles = -7;
gb->dma_current_dest = 0;
gb->dma_current_src = value << 8;
gb->dma_steps_left = 0xa0;
gb->io_registers[GB_IO_DMA] = value;
return; return;
case GB_IO_SVBK: case GB_IO_SVBK:
if (!gb->cgb_mode) { if (!gb->cgb_mode) {
@ -701,7 +696,14 @@ void GB_dma_run(GB_gameboy_t *gb)
/* Todo: measure this value */ /* Todo: measure this value */
gb->dma_cycles -= 4; gb->dma_cycles -= 4;
gb->dma_steps_left--; gb->dma_steps_left--;
gb->oam[gb->dma_current_dest++] = GB_read_memory(gb, gb->dma_current_src); if (gb->dma_current_src < 0xe000) {
gb->oam[gb->dma_current_dest++] = GB_read_memory(gb, gb->dma_current_src);
}
else {
/* Todo: Not correct on the CGB */
gb->oam[gb->dma_current_dest++] = GB_read_memory(gb, gb->dma_current_src & ~0x2000);
}
/* dma_current_src must be the correct value during GB_read_memory */ /* dma_current_src must be the correct value during GB_read_memory */
gb->dma_current_src++; gb->dma_current_src++;
if (!gb->dma_steps_left) { if (!gb->dma_steps_left) {