Fix several potential regressions
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36e2896ec7
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@ -145,6 +145,7 @@ static void cycle_write(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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/* The DMG STAT-write bug is basically the STAT register being read as FF for a single T-cycle */
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case GB_CONFLICT_STAT_DMG:
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GB_advance_cycles(gb, gb->pending_cycles);
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GB_display_sync(gb);
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/* State 7 is the edge between HBlank and OAM mode, and it behaves a bit weird.
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The OAM interrupt seems to be blocked by HBlank interrupts in that case, despite
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the timing not making much sense for that.
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@ -206,7 +207,7 @@ static void cycle_write(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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uint8_t old_value = GB_read_memory(gb, addr);
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GB_advance_cycles(gb, gb->pending_cycles - 2);
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GB_display_sync(gb);
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if (gb->model != GB_MODEL_MGB && gb->position_in_line == 0 && (old_value & 2) && !(value & 2)) {
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old_value &= ~2;
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}
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@ -277,6 +278,7 @@ static void cycle_write(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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GB_advance_cycles(gb, gb->pending_cycles);
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if (gb->model <= GB_MODEL_CGB_C) {
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// TODO: Double speed mode? This logic is also a bit weird, it needs more tests
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GB_apu_run(gb, true);
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if (gb->apu.square_sweep_calculate_countdown > 3 && gb->apu.enable_zombie_calculate_stepping) {
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gb->apu.square_sweep_calculate_countdown -= 2;
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}
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