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LCDC write timing regression fix

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This commit is contained in:
Lior Halphon 2020-12-12 22:55:14 +02:00
parent db483ce95f
commit 7a3ebb708c
1 changed files with 2 additions and 0 deletions
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2
Core/sm83_cpu.c
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@ -249,6 +249,7 @@ static void cycle_write(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
// Todo: This is difference is because my timing is off in one of the models // Todo: This is difference is because my timing is off in one of the models
if (gb->model > GB_MODEL_CGB_C) { if (gb->model > GB_MODEL_CGB_C) {
GB_advance_cycles(gb, gb->pending_cycles); GB_advance_cycles(gb, gb->pending_cycles);
GB_write_memory(gb, addr, value ^ 0x10); // Write with the old TILE_SET first
gb->tile_sel_glitch = true; gb->tile_sel_glitch = true;
GB_advance_cycles(gb, 1); GB_advance_cycles(gb, 1);
gb->tile_sel_glitch = false; gb->tile_sel_glitch = false;
@ -257,6 +258,7 @@ static void cycle_write(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
} }
else { else {
GB_advance_cycles(gb, gb->pending_cycles - 1); GB_advance_cycles(gb, gb->pending_cycles - 1);
GB_write_memory(gb, addr, value ^ 0x10); // Write with the old TILE_SET first
gb->tile_sel_glitch = true; gb->tile_sel_glitch = true;
GB_advance_cycles(gb, 1); GB_advance_cycles(gb, 1);
gb->tile_sel_glitch = false; gb->tile_sel_glitch = false;