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Refine TILE_SEL glitch, fixes #445

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This commit is contained in:
Lior Halphon 2022-06-12 21:43:04 +03:00
parent b932f6699e
commit 9b5dc9eca7
1 changed files with 1 additions and 1 deletions
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2
Core/sm83_cpu.c
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@ -242,7 +242,7 @@ static void cycle_write(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
break;
case GB_CONFLICT_CGB_LCDC:
if ((value ^ gb->io_registers[GB_IO_LCDC]) & 0x10) {
if ((~value & gb->io_registers[GB_IO_LCDC]) & 0x10) {
// Todo: This is difference is because my timing is off in one of the models
if (gb->model > GB_MODEL_CGB_C) {
GB_advance_cycles(gb, gb->pending_cycles);