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Fixed NR51 volume levels (They’re 1-8, not 0-7)

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This commit is contained in:
Lior Halphon 2018-01-06 11:58:07 +02:00
parent d62ff4eb75
commit a1af4c59ca
2 changed files with 5 additions and 5 deletions
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4
Core/apu.c
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@ -27,11 +27,11 @@ static void update_sample(GB_gameboy_t *gb, unsigned index, uint8_t value, unsig
if (gb->apu_output.sample_rate) {
unsigned left_volume = 0;
if (gb->io_registers[GB_IO_NR51] & (1 << index)) {
left_volume = gb->io_registers[GB_IO_NR50] & 7;
left_volume = (gb->io_registers[GB_IO_NR50] & 7) + 1;
}
unsigned right_volume = 0;
if (gb->io_registers[GB_IO_NR51] & (0x10 << index)) {
right_volume = (gb->io_registers[GB_IO_NR50] >> 4) & 7;
right_volume = ((gb->io_registers[GB_IO_NR50] >> 4) & 7) + 1;
}
GB_sample_t output = {(0xf - value) * left_volume, (0xf - value) * right_volume};
if (*(uint32_t *)&(gb->apu_output.current_sample[index]) != *(uint32_t *)&output) {

6
Core/apu.h
View File

@ -6,9 +6,9 @@
#ifdef GB_INTERNAL
/* Divides nicely and never overflows with 4 channels and 8 volume levels */
#define MAX_CH_AMP 0x1FFE
#define CH_STEP (MAX_CH_AMP/0xF/7)
/* Divides nicely and never overflows with 4 channels and 8 (1-8) volume levels */
#define MAX_CH_AMP 0x1FE0
#define CH_STEP (MAX_CH_AMP/0xF/8)
#endif
/* APU ticks are 2MHz, triggered by an internal APU clock. */