744 lines
26 KiB
C
744 lines
26 KiB
C
#include <stdio.h>
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#include <stdbool.h>
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#include "gb.h"
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typedef uint8_t GB_read_function_t(GB_gameboy_t *gb, uint16_t addr);
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typedef void GB_write_function_t(GB_gameboy_t *gb, uint16_t addr, uint8_t value);
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typedef enum {
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GB_BUS_MAIN, /* In DMG: Cart and RAM. In CGB: Cart only */
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GB_BUS_RAM, /* In CGB only. */
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GB_BUS_VRAM,
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GB_BUS_INTERNAL, /* Anything in highram. Might not be the most correct name. */
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} GB_bus_t;
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static GB_bus_t bus_for_addr(GB_gameboy_t *gb, uint16_t addr)
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{
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if (addr < 0x8000) {
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return GB_BUS_MAIN;
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}
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if (addr < 0xA000) {
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return GB_BUS_VRAM;
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}
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if (addr < 0xC000) {
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return GB_BUS_MAIN;
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}
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if (addr < 0xFE00) {
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return gb->is_cgb? GB_BUS_RAM : GB_BUS_MAIN;
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}
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return GB_BUS_INTERNAL;
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}
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static bool is_addr_in_dma_use(GB_gameboy_t *gb, uint16_t addr)
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{
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if (!gb->dma_steps_left || (gb->dma_cycles < 0 && !gb->is_dma_restarting) || addr >= 0xFE00) return false;
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return bus_for_addr(gb, addr) == bus_for_addr(gb, gb->dma_current_src);
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}
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static uint8_t read_rom(GB_gameboy_t *gb, uint16_t addr)
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{
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if (addr < 0x100 && !gb->boot_rom_finished) {
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return gb->boot_rom[addr];
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}
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if (addr >= 0x200 && addr < 0x900 && gb->is_cgb && !gb->boot_rom_finished) {
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return gb->boot_rom[addr];
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}
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if (!gb->rom_size) {
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return 0xFF;
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}
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unsigned int effective_address = (addr & 0x3FFF) + gb->mbc_rom0_bank * 0x4000;
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return gb->rom[effective_address & (gb->rom_size - 1)];
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}
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static uint8_t read_mbc_rom(GB_gameboy_t *gb, uint16_t addr)
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{
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unsigned int effective_address = (addr & 0x3FFF) + gb->mbc_rom_bank * 0x4000;
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return gb->rom[effective_address & (gb->rom_size - 1)];
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}
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static uint8_t read_vram(GB_gameboy_t *gb, uint16_t addr)
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{
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if (gb->vram_read_blocked) {
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return 0xFF;
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}
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return gb->vram[(addr & 0x1FFF) + (uint16_t) gb->cgb_vram_bank * 0x2000];
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}
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static uint8_t read_mbc_ram(GB_gameboy_t *gb, uint16_t addr)
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{
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if ((!gb->mbc_ram_enable || !gb->mbc_ram_size) &&
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gb->cartridge_type->mbc_subtype != GB_CAMERA &&
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gb->cartridge_type->mbc_type != GB_HUC1) return 0xFF;
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if (gb->cartridge_type->has_rtc && gb->mbc_ram_bank >= 8 && gb->mbc_ram_bank <= 0xC) {
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/* RTC read */
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gb->rtc_latched.high |= ~0xC1; /* Not all bytes in RTC high are used. */
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return gb->rtc_latched.data[gb->mbc_ram_bank - 8];
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}
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if (gb->camera_registers_mapped) {
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return GB_camera_read_register(gb, addr);
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}
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if (!gb->mbc_ram) {
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return 0xFF;
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}
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if (gb->cartridge_type->mbc_subtype == GB_CAMERA && gb->mbc_ram_bank == 0 && addr >= 0xa100 && addr < 0xaf00) {
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return GB_camera_read_image(gb, addr - 0xa100);
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}
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uint8_t ret = gb->mbc_ram[((addr & 0x1FFF) + gb->mbc_ram_bank * 0x2000) & (gb->mbc_ram_size - 1)];
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if (gb->cartridge_type->mbc_type == GB_MBC2) {
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ret |= 0xF0;
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}
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return ret;
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}
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static uint8_t read_ram(GB_gameboy_t *gb, uint16_t addr)
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{
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return gb->ram[addr & 0x0FFF];
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}
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static uint8_t read_banked_ram(GB_gameboy_t *gb, uint16_t addr)
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{
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return gb->ram[(addr & 0x0FFF) + gb->cgb_ram_bank * 0x1000];
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}
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static uint8_t read_high_memory(GB_gameboy_t *gb, uint16_t addr)
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{
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if (gb->hdma_on) {
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return gb->last_opcode_read;
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}
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if (addr < 0xFE00) {
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return gb->ram[addr & 0x0FFF];
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}
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if (addr < 0xFEA0) {
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if (gb->oam_read_blocked || (gb->dma_steps_left && (gb->dma_cycles > 0 || gb->is_dma_restarting))) {
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return 0xFF;
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}
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return gb->oam[addr & 0xFF];
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}
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if (addr < 0xFF00) {
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/* Unusable. CGB results are verified, but DMG results were tested on a SGB2 */
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/* Also, writes to this area are not emulated */
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if ((gb->io_registers[GB_IO_STAT] & 0x3) >= 2) { /* Seems to be disabled in Modes 2 and 3 */
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return 0xFF;
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}
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if (gb->is_cgb) {
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return (addr & 0xF0) | ((addr >> 4) & 0xF);
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}
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return 0;
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}
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if (addr < 0xFF80) {
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switch (addr & 0xFF) {
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case GB_IO_IF:
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return gb->io_registers[GB_IO_IF] | 0xE0;
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case GB_IO_TAC:
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return gb->io_registers[GB_IO_TAC] | 0xF8;
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case GB_IO_STAT:
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return gb->io_registers[GB_IO_STAT] | 0x80;
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case GB_IO_DMG_EMULATION_INDICATION:
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if (!gb->cgb_mode) {
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return 0xFF;
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}
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return gb->io_registers[GB_IO_DMG_EMULATION_INDICATION] | 0xFE;
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case GB_IO_PCM_12:
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if (!gb->is_cgb) return 0xFF;
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return (gb->apu.is_active[GB_SQUARE_2] ? (gb->apu.samples[GB_SQUARE_2] << 4) : 0) |
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(gb->apu.is_active[GB_SQUARE_1] ? (gb->apu.samples[GB_SQUARE_1]) : 0);
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case GB_IO_PCM_34:
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if (!gb->is_cgb) return 0xFF;
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return (gb->apu.is_active[GB_NOISE] ? (gb->apu.samples[GB_NOISE] << 4) : 0) |
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(gb->apu.is_active[GB_WAVE] ? (gb->apu.samples[GB_WAVE]) : 0);
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case GB_IO_JOYP:
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case GB_IO_TMA:
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case GB_IO_LCDC:
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case GB_IO_SCY:
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case GB_IO_SCX:
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case GB_IO_LY:
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case GB_IO_LYC:
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case GB_IO_BGP:
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case GB_IO_OBP0:
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case GB_IO_OBP1:
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case GB_IO_WY:
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case GB_IO_WX:
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case GB_IO_SC:
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case GB_IO_SB:
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case GB_IO_DMA:
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return gb->io_registers[addr & 0xFF];
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case GB_IO_TIMA:
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if (gb->tima_reload_state == GB_TIMA_RELOADING) {
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return 0;
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}
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return gb->io_registers[GB_IO_TIMA];
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case GB_IO_DIV:
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return gb->div_counter >> 8;
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case GB_IO_HDMA5:
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if (!gb->cgb_mode) return 0xFF;
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return ((gb->hdma_on || gb->hdma_on_hblank)? 0 : 0x80) | ((gb->hdma_steps_left - 1) & 0x7F);
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case GB_IO_SVBK:
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if (!gb->cgb_mode) {
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return 0xFF;
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}
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return gb->cgb_ram_bank | ~0x7;
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case GB_IO_VBK:
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if (!gb->is_cgb) {
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return 0xFF;
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}
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return gb->cgb_vram_bank | ~0x1;
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/* Todo: It seems that a CGB in DMG mode can access BGPI and OBPI, but not BGPD and OBPD? */
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case GB_IO_BGPI:
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case GB_IO_OBPI:
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if (!gb->is_cgb) {
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return 0xFF;
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}
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return gb->io_registers[addr & 0xFF] | 0x40;
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case GB_IO_BGPD:
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case GB_IO_OBPD:
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{
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if (!gb->cgb_mode && gb->boot_rom_finished) {
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return 0xFF;
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}
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uint8_t index_reg = (addr & 0xFF) - 1;
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return ((addr & 0xFF) == GB_IO_BGPD?
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gb->background_palettes_data :
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gb->sprite_palettes_data)[gb->io_registers[index_reg] & 0x3F];
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}
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case GB_IO_KEY1:
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if (!gb->cgb_mode) {
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return 0xFF;
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}
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return (gb->io_registers[GB_IO_KEY1] & 0x7F) | (gb->cgb_double_speed? 0xFE : 0x7E);
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case GB_IO_RP: {
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if (!gb->cgb_mode) return 0xFF;
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/* You will read your own IR LED if it's on. */
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bool read_value = gb->infrared_input || (gb->io_registers[GB_IO_RP] & 1);
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uint8_t ret = (gb->io_registers[GB_IO_RP] & 0xC1) | 0x3C;
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if ((gb->io_registers[GB_IO_RP] & 0xC0) == 0xC0 && read_value) {
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ret |= 2;
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}
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return ret;
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}
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case GB_IO_UNKNOWN2:
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case GB_IO_UNKNOWN3:
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return gb->is_cgb? gb->io_registers[addr & 0xFF] : 0xFF;
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case GB_IO_UNKNOWN4:
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return gb->cgb_mode? gb->io_registers[addr & 0xFF] : 0xFF;
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case GB_IO_UNKNOWN5:
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return gb->is_cgb? gb->io_registers[addr & 0xFF] | 0x8F : 0xFF;
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default:
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if ((addr & 0xFF) >= GB_IO_NR10 && (addr & 0xFF) <= GB_IO_WAV_END) {
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return GB_apu_read(gb, addr & 0xFF);
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}
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return 0xFF;
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}
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/* Hardware registers */
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return 0;
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}
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if (addr == 0xFFFF) {
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/* Interrupt Mask */
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return gb->interrupt_enable;
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}
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/* HRAM */
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return gb->hram[addr - 0xFF80];
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}
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static GB_read_function_t * const read_map[] =
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{
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read_rom, read_rom, read_rom, read_rom, /* 0XXX, 1XXX, 2XXX, 3XXX */
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read_mbc_rom, read_mbc_rom, read_mbc_rom, read_mbc_rom, /* 4XXX, 5XXX, 6XXX, 7XXX */
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read_vram, read_vram, /* 8XXX, 9XXX */
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read_mbc_ram, read_mbc_ram, /* AXXX, BXXX */
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read_ram, read_banked_ram, /* CXXX, DXXX */
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read_high_memory, read_high_memory, /* EXXX FXXX */
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};
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uint8_t GB_read_memory(GB_gameboy_t *gb, uint16_t addr)
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{
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if (gb->n_watchpoints) {
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GB_debugger_test_read_watchpoint(gb, addr);
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}
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if (is_addr_in_dma_use(gb, addr)) {
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addr = gb->dma_current_src;
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}
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return read_map[addr >> 12](gb, addr);
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}
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static void write_mbc(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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{
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switch (gb->cartridge_type->mbc_type) {
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case GB_NO_MBC: return;
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case GB_MBC1:
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switch (addr & 0xF000) {
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case 0x0000: case 0x1000: gb->mbc_ram_enable = (value & 0xF) == 0xA; break;
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case 0x2000: case 0x3000: gb->mbc1.bank_low = value; break;
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case 0x4000: case 0x5000: gb->mbc1.bank_high = value; break;
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case 0x6000: case 0x7000: gb->mbc1.mode = value; break;
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}
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break;
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case GB_MBC2:
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switch (addr & 0xF000) {
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case 0x0000: case 0x1000: if (!(addr & 0x100)) gb->mbc_ram_enable = (value & 0xF) == 0xA; break;
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case 0x2000: case 0x3000: if ( addr & 0x100) gb->mbc2.rom_bank = value; break;
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}
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break;
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case GB_MBC3:
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switch (addr & 0xF000) {
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case 0x0000: case 0x1000: gb->mbc_ram_enable = (value & 0xF) == 0xA; break;
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case 0x2000: case 0x3000: gb->mbc3.rom_bank = value; break;
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case 0x4000: case 0x5000: gb->mbc3.ram_bank = value; break;
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case 0x6000: case 0x7000:
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if (!gb->rtc_latch && (value & 1)) { /* Todo: verify condition is correct */
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memcpy(&gb->rtc_latched, &gb->rtc_real, sizeof(gb->rtc_real));
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}
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gb->rtc_latch = value & 1;
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break;
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}
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break;
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case GB_MBC5:
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switch (addr & 0xF000) {
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case 0x0000: case 0x1000: gb->mbc_ram_enable = (value & 0xF) == 0xA; break;
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case 0x2000: gb->mbc5.rom_bank_low = value; break;
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case 0x3000: gb->mbc5.rom_bank_high = value; break;
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case 0x4000: case 0x5000:
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if (gb->cartridge_type->has_rumble) {
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if (!!(value & 8) != gb->rumble_state) {
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gb->rumble_state = !gb->rumble_state;
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if (gb->rumble_callback) {
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gb->rumble_callback(gb, gb->rumble_state);
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}
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}
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value &= 7;
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}
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gb->mbc5.ram_bank = value;
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gb->camera_registers_mapped = (value & 0x10) && gb->cartridge_type->mbc_subtype == GB_CAMERA;
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break;
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}
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break;
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case GB_HUC1:
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switch (addr & 0xF000) {
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case 0x0000: case 0x1000: gb->mbc_ram_enable = (value & 0xF) == 0xA; break;
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case 0x2000: case 0x3000: gb->huc1.bank_low = value; break;
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case 0x4000: case 0x5000: gb->huc1.bank_high = value; break;
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case 0x6000: case 0x7000: gb->huc1.mode = value; break;
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}
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break;
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case GB_HUC3:
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switch (addr & 0xF000) {
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case 0x0000: case 0x1000: gb->mbc_ram_enable = (value & 0xF) == 0xA; break;
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case 0x2000: case 0x3000: gb->huc3.rom_bank = value; break;
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case 0x4000: case 0x5000: gb->huc3.ram_bank = value; break;
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}
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break;
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}
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GB_update_mbc_mappings(gb);
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}
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static void write_vram(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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{
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if (gb->vram_write_blocked) {
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//GB_log(gb, "Wrote %02x to %04x (VRAM) during mode 3\n", value, addr);
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return;
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}
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gb->vram[(addr & 0x1FFF) + (uint16_t) gb->cgb_vram_bank * 0x2000] = value;
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}
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static void write_mbc_ram(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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{
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if (gb->camera_registers_mapped) {
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GB_camera_write_register(gb, addr, value);
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return;
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}
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if (!gb->mbc_ram_enable || !gb->mbc_ram_size) return;
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if (gb->cartridge_type->has_rtc && gb->mbc_ram_bank >= 8 && gb->mbc_ram_bank <= 0xC) {
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/* RTC read */
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gb->rtc_latched.data[gb->mbc_ram_bank - 8] = gb->rtc_real.data[gb->mbc_ram_bank - 8] = value; /* Todo: does it really write both? */
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}
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if (!gb->mbc_ram) {
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return;
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}
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gb->mbc_ram[((addr & 0x1FFF) + gb->mbc_ram_bank * 0x2000) & (gb->mbc_ram_size - 1)] = value;
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}
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static void write_ram(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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{
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gb->ram[addr & 0x0FFF] = value;
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}
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static void write_banked_ram(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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{
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gb->ram[(addr & 0x0FFF) + gb->cgb_ram_bank * 0x1000] = value;
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}
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static void write_high_memory(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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{
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if (addr < 0xFE00) {
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GB_log(gb, "Wrote %02x to %04x (RAM Mirror)\n", value, addr);
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gb->ram[addr & 0x0FFF] = value;
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return;
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}
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if (addr < 0xFEA0) {
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if (gb->oam_write_blocked|| (gb->dma_steps_left && (gb->dma_cycles > 0 || gb->is_dma_restarting))) {
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return;
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}
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gb->oam[addr & 0xFF] = value;
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return;
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}
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if (addr < 0xFF00) {
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GB_log(gb, "Wrote %02x to %04x (Unused)\n", value, addr);
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return;
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}
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/* Todo: Clean this code up: use a function table and move relevant code to display.c and timing.c
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(APU read and writes are already at apu.c) */
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if (addr < 0xFF80) {
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/* Hardware registers */
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switch (addr & 0xFF) {
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case GB_IO_WX:
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GB_window_related_write(gb, addr & 0xFF, value);
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break;
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case GB_IO_IF:
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case GB_IO_SCX:
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case GB_IO_SCY:
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case GB_IO_BGP:
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case GB_IO_OBP0:
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case GB_IO_OBP1:
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case GB_IO_WY:
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case GB_IO_SB:
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case GB_IO_DMG_EMULATION_INDICATION:
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case GB_IO_UNKNOWN2:
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case GB_IO_UNKNOWN3:
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case GB_IO_UNKNOWN4:
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case GB_IO_UNKNOWN5:
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gb->io_registers[addr & 0xFF] = value;
|
|
return;
|
|
case GB_IO_LYC:
|
|
gb->io_registers[addr & 0xFF] = value;
|
|
GB_STAT_update(gb);
|
|
return;
|
|
|
|
case GB_IO_TIMA:
|
|
if (gb->tima_reload_state != GB_TIMA_RELOADED) {
|
|
gb->io_registers[GB_IO_TIMA] = value;
|
|
}
|
|
return;
|
|
|
|
case GB_IO_TMA:
|
|
gb->io_registers[GB_IO_TMA] = value;
|
|
if (gb->tima_reload_state != GB_TIMA_RUNNING) {
|
|
gb->io_registers[GB_IO_TIMA] = value;
|
|
}
|
|
return;
|
|
|
|
case GB_IO_TAC:
|
|
GB_emulate_timer_glitch(gb, gb->io_registers[GB_IO_TAC], value);
|
|
gb->io_registers[GB_IO_TAC] = value;
|
|
return;
|
|
|
|
|
|
case GB_IO_LCDC:
|
|
if ((value & 0x80) && !(gb->io_registers[GB_IO_LCDC] & 0x80)) {
|
|
gb->display_cycles = 0;
|
|
gb->display_state = 0;
|
|
if (gb->frame_skip_state == GB_FRAMESKIP_SECOND_FRAME_RENDERED) {
|
|
gb->frame_skip_state = GB_FRAMESKIP_LCD_TURNED_ON;
|
|
}
|
|
}
|
|
else if (!(value & 0x80) && (gb->io_registers[GB_IO_LCDC] & 0x80)) {
|
|
/* Sync after turning off LCD */
|
|
GB_timing_sync(gb);
|
|
GB_lcd_off(gb);
|
|
}
|
|
/* Writing to LCDC might enable to disable the window, so we write it via GB_window_related_write */
|
|
GB_window_related_write(gb, addr & 0xFF, value);
|
|
return;
|
|
|
|
case GB_IO_STAT:
|
|
/* A DMG bug: http://www.devrs.com/gb/files/faqs.html#GBBugs */
|
|
if (!gb->is_cgb && !gb->stat_interrupt_line &&
|
|
(gb->io_registers[GB_IO_STAT] & 0x3) < 2 && (gb->io_registers[GB_IO_LCDC] & 0x80)) {
|
|
gb->io_registers[GB_IO_IF] |= 2;
|
|
}
|
|
/* Delete previous R/W bits */
|
|
gb->io_registers[GB_IO_STAT] &= 7;
|
|
/* Set them by value */
|
|
gb->io_registers[GB_IO_STAT] |= value & ~7;
|
|
/* Set unused bit to 1 */
|
|
gb->io_registers[GB_IO_STAT] |= 0x80;
|
|
|
|
GB_STAT_update(gb);
|
|
return;
|
|
|
|
case GB_IO_DIV:
|
|
/* Reset the div state machine */
|
|
gb->div_state = 0;
|
|
gb->div_cycles = 0;
|
|
return;
|
|
|
|
case GB_IO_JOYP:
|
|
gb->io_registers[GB_IO_JOYP] &= 0x0F;
|
|
gb->io_registers[GB_IO_JOYP] |= value & 0xF0;
|
|
GB_update_joyp(gb);
|
|
return;
|
|
|
|
case GB_IO_BIOS:
|
|
gb->boot_rom_finished = true;
|
|
return;
|
|
|
|
case GB_IO_DMG_EMULATION:
|
|
if (gb->is_cgb && !gb->boot_rom_finished) {
|
|
gb->cgb_mode = value != 4; /* The real "contents" of this register aren't quite known yet. */
|
|
}
|
|
return;
|
|
|
|
case GB_IO_DMA:
|
|
if (gb->dma_steps_left) {
|
|
/* This is not correct emulation, since we're not really delaying the second DMA.
|
|
One write that should have happened in the first DMA will not happen. However,
|
|
since that byte will be overwritten by the second DMA before it can actually be
|
|
read, it doesn't actually matter. */
|
|
gb->is_dma_restarting = true;
|
|
}
|
|
gb->dma_cycles = -7;
|
|
gb->dma_current_dest = 0;
|
|
gb->dma_current_src = value << 8;
|
|
gb->dma_steps_left = 0xa0;
|
|
gb->io_registers[GB_IO_DMA] = value;
|
|
return;
|
|
case GB_IO_SVBK:
|
|
if (!gb->cgb_mode) {
|
|
return;
|
|
}
|
|
gb->cgb_ram_bank = value & 0x7;
|
|
if (!gb->cgb_ram_bank) {
|
|
gb->cgb_ram_bank++;
|
|
}
|
|
return;
|
|
case GB_IO_VBK:
|
|
if (!gb->cgb_mode) {
|
|
return;
|
|
}
|
|
gb->cgb_vram_bank = value & 0x1;
|
|
return;
|
|
|
|
case GB_IO_BGPI:
|
|
case GB_IO_OBPI:
|
|
if (!gb->is_cgb) {
|
|
return;
|
|
}
|
|
gb->io_registers[addr & 0xFF] = value;
|
|
return;
|
|
case GB_IO_BGPD:
|
|
case GB_IO_OBPD:
|
|
if (!gb->cgb_mode && gb->boot_rom_finished) {
|
|
/* Todo: Due to the behavior of a broken Game & Watch Gallery 2 ROM on a real CGB. A proper test ROM
|
|
is required. */
|
|
return;
|
|
}
|
|
uint8_t index_reg = (addr & 0xFF) - 1;
|
|
((addr & 0xFF) == GB_IO_BGPD?
|
|
gb->background_palettes_data :
|
|
gb->sprite_palettes_data)[gb->io_registers[index_reg] & 0x3F] = value;
|
|
GB_palette_changed(gb, (addr & 0xFF) == GB_IO_BGPD, gb->io_registers[index_reg] & 0x3F);
|
|
if (gb->io_registers[index_reg] & 0x80) {
|
|
gb->io_registers[index_reg]++;
|
|
gb->io_registers[index_reg] |= 0x80;
|
|
}
|
|
return;
|
|
case GB_IO_KEY1:
|
|
if (!gb->cgb_mode) {
|
|
return;
|
|
}
|
|
gb->io_registers[GB_IO_KEY1] = value;
|
|
return;
|
|
case GB_IO_HDMA1:
|
|
if (gb->cgb_mode) {
|
|
gb->hdma_current_src &= 0xF0;
|
|
gb->hdma_current_src |= value << 8;
|
|
}
|
|
return;
|
|
case GB_IO_HDMA2:
|
|
if (gb->cgb_mode) {
|
|
gb->hdma_current_src &= 0xFF00;
|
|
gb->hdma_current_src |= value & 0xF0;
|
|
}
|
|
return;
|
|
case GB_IO_HDMA3:
|
|
if (gb->cgb_mode) {
|
|
gb->hdma_current_dest &= 0xF0;
|
|
gb->hdma_current_dest |= value << 8;
|
|
}
|
|
return;
|
|
case GB_IO_HDMA4:
|
|
if (gb->cgb_mode) {
|
|
gb->hdma_current_dest &= 0x1F00;
|
|
gb->hdma_current_dest |= value & 0xF0;
|
|
}
|
|
return;
|
|
case GB_IO_HDMA5:
|
|
if (!gb->cgb_mode) return;
|
|
if ((value & 0x80) == 0 && gb->hdma_on_hblank) {
|
|
gb->hdma_on_hblank = false;
|
|
return;
|
|
}
|
|
gb->hdma_on = (value & 0x80) == 0;
|
|
gb->hdma_on_hblank = (value & 0x80) != 0;
|
|
if (gb->hdma_on_hblank && (gb->io_registers[GB_IO_STAT] & 3) == 0) {
|
|
gb->hdma_on = true;
|
|
gb->hdma_cycles = 0;
|
|
}
|
|
gb->io_registers[GB_IO_HDMA5] = value;
|
|
gb->hdma_steps_left = (gb->io_registers[GB_IO_HDMA5] & 0x7F) + 1;
|
|
/* Todo: Verify this. Gambatte's DMA tests require this. */
|
|
if (gb->hdma_current_dest + (gb->hdma_steps_left << 4) > 0xFFFF) {
|
|
gb->hdma_steps_left = (0x10000 - gb->hdma_current_dest) >> 4;
|
|
}
|
|
gb->hdma_cycles = 0;
|
|
return;
|
|
|
|
/* Todo: what happens when starting a transfer during a transfer?
|
|
What happens when starting a transfer during external clock?
|
|
*/
|
|
case GB_IO_SC:
|
|
if (!gb->cgb_mode) {
|
|
value |= 2;
|
|
}
|
|
gb->io_registers[GB_IO_SC] = value | (~0x83);
|
|
if ((value & 0x80) && (value & 0x1) ) {
|
|
gb->serial_length = gb->cgb_mode && (value & 2)? 128 : 4096;
|
|
/* Todo: This is probably incorrect for CGB's faster clock mode. */
|
|
gb->serial_cycles &= 0xFF;
|
|
if (gb->serial_transfer_start_callback) {
|
|
gb->serial_transfer_start_callback(gb, gb->io_registers[GB_IO_SB]);
|
|
}
|
|
}
|
|
else {
|
|
gb->serial_length = 0;
|
|
}
|
|
return;
|
|
|
|
case GB_IO_RP: {
|
|
if (!gb->is_cgb) {
|
|
return;
|
|
}
|
|
if ((value & 1) != (gb->io_registers[GB_IO_RP] & 1)) {
|
|
if (gb->infrared_callback) {
|
|
gb->infrared_callback(gb, value & 1, gb->cycles_since_ir_change);
|
|
gb->cycles_since_ir_change = 0;
|
|
}
|
|
}
|
|
gb->io_registers[GB_IO_RP] = value;
|
|
return;
|
|
}
|
|
|
|
default:
|
|
if ((addr & 0xFF) >= GB_IO_NR10 && (addr & 0xFF) <= GB_IO_WAV_END) {
|
|
GB_apu_write(gb, addr & 0xFF, value);
|
|
return;
|
|
}
|
|
GB_log(gb, "Wrote %02x to %04x (HW Register)\n", value, addr);
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (addr == 0xFFFF) {
|
|
/* Interrupt mask */
|
|
gb->interrupt_enable = value;
|
|
return;
|
|
}
|
|
|
|
/* HRAM */
|
|
gb->hram[addr - 0xFF80] = value;
|
|
}
|
|
|
|
|
|
|
|
static GB_write_function_t * const write_map[] =
|
|
{
|
|
write_mbc, write_mbc, write_mbc, write_mbc, /* 0XXX, 1XXX, 2XXX, 3XXX */
|
|
write_mbc, write_mbc, write_mbc, write_mbc, /* 4XXX, 5XXX, 6XXX, 7XXX */
|
|
write_vram, write_vram, /* 8XXX, 9XXX */
|
|
write_mbc_ram, write_mbc_ram, /* AXXX, BXXX */
|
|
write_ram, write_banked_ram, /* CXXX, DXXX */
|
|
write_high_memory, write_high_memory, /* EXXX FXXX */
|
|
};
|
|
|
|
void GB_write_memory(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
|
|
{
|
|
if (gb->n_watchpoints) {
|
|
GB_debugger_test_write_watchpoint(gb, addr, value);
|
|
}
|
|
if (is_addr_in_dma_use(gb, addr)) {
|
|
/* Todo: What should happen? Will this affect DMA? Will data be written? What and where? */
|
|
return;
|
|
}
|
|
write_map[addr >> 12](gb, addr, value);
|
|
}
|
|
|
|
void GB_dma_run(GB_gameboy_t *gb)
|
|
{
|
|
while (gb->dma_cycles >= 4 && gb->dma_steps_left) {
|
|
/* Todo: measure this value */
|
|
gb->dma_cycles -= 4;
|
|
gb->dma_steps_left--;
|
|
if (gb->dma_current_src < 0xe000) {
|
|
gb->oam[gb->dma_current_dest++] = GB_read_memory(gb, gb->dma_current_src);
|
|
}
|
|
else {
|
|
/* Todo: Not correct on the CGB */
|
|
gb->oam[gb->dma_current_dest++] = GB_read_memory(gb, gb->dma_current_src & ~0x2000);
|
|
}
|
|
|
|
/* dma_current_src must be the correct value during GB_read_memory */
|
|
gb->dma_current_src++;
|
|
if (!gb->dma_steps_left) {
|
|
gb->is_dma_restarting = false;
|
|
}
|
|
}
|
|
}
|
|
|
|
void GB_hdma_run(GB_gameboy_t *gb)
|
|
{
|
|
if (!gb->hdma_on) return;
|
|
while (gb->hdma_cycles >= 0x10) {
|
|
gb->hdma_cycles -= 0x10;
|
|
|
|
for (uint8_t i = 0; i < 0x10; i++) {
|
|
GB_write_memory(gb, 0x8000 | (gb->hdma_current_dest++ & 0x1FFF), GB_read_memory(gb, (gb->hdma_current_src++)));
|
|
}
|
|
|
|
if(--gb->hdma_steps_left == 0){
|
|
gb->hdma_on = false;
|
|
gb->hdma_on_hblank = false;
|
|
gb->io_registers[GB_IO_HDMA5] &= 0x7F;
|
|
break;
|
|
}
|
|
if (gb->hdma_on_hblank) {
|
|
gb->hdma_on = false;
|
|
break;
|
|
}
|
|
}
|
|
}
|