147 lines
4.4 KiB
C
147 lines
4.4 KiB
C
#ifndef apu_h
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#define apu_h
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#include <stdbool.h>
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#include <stdint.h>
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#include "gb_struct_def.h"
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#ifdef GB_INTERNAL
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/* Divides nicely and never overflows with 4 channels and 8 volume levels */
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#define MAX_CH_AMP 0x1FFE
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#define CH_STEP (MAX_CH_AMP/0xF/7)
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#endif
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/* APU ticks are 2MHz, triggered by an internal APU clock. */
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typedef struct
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{
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int16_t left;
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int16_t right;
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} GB_sample_t;
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typedef struct
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{
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double left;
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double right;
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} GB_double_sample_t;
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enum GB_CHANNELS {
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GB_SQUARE_1,
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GB_SQUARE_2,
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GB_WAVE,
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GB_NOISE,
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GB_N_CHANNELS
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};
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typedef struct
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{
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bool global_enable;
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uint8_t apu_cycles;
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uint8_t samples[GB_N_CHANNELS];
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bool is_active[GB_N_CHANNELS];
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uint8_t div_divider; // The DIV register ticks the APU at 512Hz, but is then divided
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// once more to generate 128Hz and 64Hz clocks
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uint8_t lf_div; // The APU runs in 2MHz, but channels 1, 2 and 4 run in 1MHZ so we divide
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// need to divide the signal.
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uint8_t square_sweep_countdown; // In 128Hz
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uint8_t square_sweep_calculate_countdown; // In 2 MHz
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uint16_t new_sweep_sample_legnth;
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uint16_t shadow_sweep_sample_legnth;
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bool sweep_enabled;
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bool sweep_decreasing;
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struct {
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uint16_t pulse_length; // Reloaded from NRX1 (xorred), in 256Hz DIV ticks
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uint8_t current_volume; // Reloaded from NRX2
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uint8_t volume_countdown; // Reloaded from NRX2
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uint8_t current_sample_index;
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uint16_t sample_countdown; // in APU ticks (Reloaded from sample_length, xorred $7FF)
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uint16_t sample_length; // From NRX3, NRX4, in APU ticks
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bool length_enabled; // NRX4
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} square_channels[2];
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struct {
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bool enable; // NR30
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uint16_t pulse_length; // Reloaded from NR31 (xorred), in 256Hz DIV ticks
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uint8_t shift; // NR32
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uint16_t sample_length; // NR33, NR34, in APU ticks
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bool length_enabled; // NR34
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uint16_t sample_countdown; // in APU ticks (Reloaded from sample_length, xorred $7FF)
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uint8_t current_sample_index;
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uint8_t current_sample; // Current sample before shifting.
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int8_t wave_form[32];
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bool wave_form_just_read;
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} wave_channel;
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struct {
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uint16_t pulse_length; // Reloaded from NR41 (xorred), in 256Hz DIV ticks
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uint8_t current_volume; // Reloaded from NR42
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uint8_t volume_countdown; // Reloaded from NR42
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uint16_t lfsr;
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bool narrow;
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uint16_t sample_countdown; // in APU ticks (Reloaded from sample_length)
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uint16_t sample_length; // From NR43, in APU ticks
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bool length_enabled; // NR44
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uint8_t alignment; // If (NR43 & 7) != 0, samples are aligned to 512KHz clock instead of
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// 1MHz. This variable keeps track of the alignment.
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} noise_channel;
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} GB_apu_t;
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typedef enum {
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GB_HIGHPASS_OFF, // Do not apply any filter, keep DC offset
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GB_HIGHPASS_ACCURATE, // Apply a highpass filter similar to the one used on hardware
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GB_HIGHPASS_REMOVE_DC_OFFSET, // Remove DC Offset without affecting the waveform
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GB_HIGHPASS_MAX
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} GB_highpass_mode_t;
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typedef struct {
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unsigned sample_rate;
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GB_sample_t *buffer;
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size_t buffer_size;
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size_t buffer_position;
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bool stream_started; /* detects first copy request to minimize lag */
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volatile bool copy_in_progress;
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volatile bool lock;
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double sample_cycles;
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// Samples are NOT normalized to MAX_CH_AMP * 4 at this stage!
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unsigned cycles_since_render;
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unsigned last_update[GB_N_CHANNELS];
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GB_sample_t current_sample[GB_N_CHANNELS];
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GB_sample_t summed_samples[GB_N_CHANNELS];
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GB_highpass_mode_t highpass_mode;
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double highpass_rate;
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GB_double_sample_t highpass_diff;
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} GB_apu_output_t;
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void GB_set_sample_rate(GB_gameboy_t *gb, unsigned int sample_rate);
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void GB_apu_copy_buffer(GB_gameboy_t *gb, GB_sample_t *dest, size_t count);
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size_t GB_apu_get_current_buffer_length(GB_gameboy_t *gb);
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void GB_set_highpass_filter_mode(GB_gameboy_t *gb, GB_highpass_mode_t mode);
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#ifdef GB_INTERNAL
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void GB_apu_write(GB_gameboy_t *gb, uint8_t reg, uint8_t value);
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uint8_t GB_apu_read(GB_gameboy_t *gb, uint8_t reg);
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void GB_apu_div_event(GB_gameboy_t *gb);
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void GB_apu_init(GB_gameboy_t *gb);
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void GB_apu_run(GB_gameboy_t *gb);
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#endif
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#endif /* apu_h */
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