380 lines
8.1 KiB
C
380 lines
8.1 KiB
C
/* Copyright (c) 2013-2016 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef GB_MEMORY_H
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#define GB_MEMORY_H
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#include <mgba-util/common.h>
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CXX_GUARD_START
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#include <mgba/core/log.h>
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#include <mgba/core/timing.h>
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#include <mgba/gb/interface.h>
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mLOG_DECLARE_CATEGORY(GB_MBC);
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mLOG_DECLARE_CATEGORY(GB_MEM);
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struct GB;
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enum {
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GB_BASE_CART_BANK0 = 0x0000,
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GB_BASE_CART_BANK1 = 0x4000,
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GB_BASE_CART_HALFBANK1 = 0x4000,
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GB_BASE_CART_HALFBANK2 = 0x6000,
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GB_BASE_VRAM = 0x8000,
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GB_BASE_EXTERNAL_RAM = 0xA000,
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GB_BASE_EXTERNAL_RAM_HALFBANK0 = 0xA000,
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GB_BASE_EXTERNAL_RAM_HALFBANK1 = 0xB000,
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GB_BASE_WORKING_RAM_BANK0 = 0xC000,
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GB_BASE_WORKING_RAM_BANK1 = 0xD000,
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GB_BASE_OAM = 0xFE00,
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GB_BASE_UNUSABLE = 0xFEA0,
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GB_BASE_IO = 0xFF00,
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GB_BASE_HRAM = 0xFF80,
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GB_BASE_IE = 0xFFFF
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};
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enum {
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GB_REGION_CART_BANK0 = 0x0,
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GB_REGION_CART_BANK1 = 0x4,
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GB_REGION_VRAM = 0x8,
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GB_REGION_EXTERNAL_RAM = 0xA,
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GB_REGION_WORKING_RAM_BANK0 = 0xC,
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GB_REGION_WORKING_RAM_BANK1 = 0xD,
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GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
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GB_REGION_OTHER = 0xF,
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};
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enum {
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GB_SIZE_CART_BANK0 = 0x4000,
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GB_SIZE_CART_HALFBANK = 0x2000,
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GB_SIZE_CART_MAX = 0x800000,
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GB_SIZE_VRAM = 0x4000,
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GB_SIZE_VRAM_BANK0 = 0x2000,
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GB_SIZE_EXTERNAL_RAM = 0x2000,
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GB_SIZE_EXTERNAL_RAM_HALFBANK = 0x1000,
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GB_SIZE_WORKING_RAM = 0x8000,
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GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
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GB_SIZE_OAM = 0xA0,
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GB_SIZE_IO = 0x80,
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GB_SIZE_HRAM = 0x7F,
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GB_SIZE_MBC6_FLASH = 0x100000,
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};
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struct GBMemory;
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typedef void (*GBMemoryBankControllerWrite)(struct GB*, uint16_t address, uint8_t value);
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typedef uint8_t (*GBMemoryBankControllerRead)(struct GBMemory*, uint16_t address);
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DECL_BITFIELD(GBMBC7Field, uint8_t);
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DECL_BIT(GBMBC7Field, CS, 7);
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DECL_BIT(GBMBC7Field, CLK, 6);
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DECL_BIT(GBMBC7Field, DI, 1);
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DECL_BIT(GBMBC7Field, DO, 0);
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enum GBMBC7MachineState {
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GBMBC7_STATE_IDLE = 0,
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GBMBC7_STATE_READ_COMMAND = 1,
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GBMBC7_STATE_DO = 2,
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GBMBC7_STATE_EEPROM_EWDS = 0x10,
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GBMBC7_STATE_EEPROM_WRAL = 0x11,
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GBMBC7_STATE_EEPROM_ERAL = 0x12,
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GBMBC7_STATE_EEPROM_EWEN = 0x13,
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GBMBC7_STATE_EEPROM_WRITE = 0x14,
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GBMBC7_STATE_EEPROM_READ = 0x18,
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GBMBC7_STATE_EEPROM_ERASE = 0x1C,
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};
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enum GBTAMA5Register {
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GBTAMA5_BANK_LO = 0x0,
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GBTAMA5_BANK_HI = 0x1,
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GBTAMA5_WRITE_LO = 0x4,
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GBTAMA5_WRITE_HI = 0x5,
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GBTAMA5_ADDR_HI = 0x6,
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GBTAMA5_ADDR_LO = 0x7,
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GBTAMA5_MAX = 0x8,
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GBTAMA5_ACTIVE = 0xA,
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GBTAMA5_READ_LO = 0xC,
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GBTAMA5_READ_HI = 0xD,
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};
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enum GBTAMA6RTCRegister {
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GBTAMA6_RTC_PA0_SECOND_1 = 0x0,
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GBTAMA6_RTC_PA0_SECOND_10 = 0x1,
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GBTAMA6_RTC_PA0_MINUTE_1 = 0x2,
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GBTAMA6_RTC_PA0_MINUTE_10 = 0x3,
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GBTAMA6_RTC_PA0_HOUR_1 = 0x4,
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GBTAMA6_RTC_PA0_HOUR_10 = 0x5,
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GBTAMA6_RTC_PA0_WEEK = 0x6,
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GBTAMA6_RTC_PA0_DAY_1 = 0x7,
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GBTAMA6_RTC_PA0_DAY_10 = 0x8,
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GBTAMA6_RTC_PA0_MONTH_1 = 0x9,
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GBTAMA6_RTC_PA0_MONTH_10 = 0xA,
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GBTAMA6_RTC_PA0_YEAR_1 = 0xB,
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GBTAMA6_RTC_PA0_YEAR_10 = 0xC,
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GBTAMA6_RTC_PA1_MINUTE_1 = 0x2,
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GBTAMA6_RTC_PA1_MINUTE_10 = 0x3,
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GBTAMA6_RTC_PA1_HOUR_1 = 0x4,
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GBTAMA6_RTC_PA1_HOUR_10 = 0x5,
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GBTAMA6_RTC_PA1_WEEK = 0x6,
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GBTAMA6_RTC_PA1_DAY_1 = 0x7,
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GBTAMA6_RTC_PA1_DAY_10 = 0x8,
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GBTAMA6_RTC_PA1_24_HOUR = 0xA,
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GBTAMA6_RTC_PA1_LEAP_YEAR = 0xB,
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GBTAMA6_RTC_PAGE = 0xD,
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GBTAMA6_RTC_TEST = 0xE,
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GBTAMA6_RTC_RESET = 0xF,
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GBTAMA6_RTC_MAX
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};
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enum GBTAMA6Command {
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GBTAMA6_DISABLE_TIMER = 0x0,
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GBTAMA6_ENABLE_TIMER = 0x1,
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GBTAMA6_MINUTE_WRITE = 0x4,
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GBTAMA6_HOUR_WRITE = 0x5,
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GBTAMA6_MINUTE_READ = 0x6,
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GBTAMA6_HOUR_READ = 0x7,
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GBTAMA6_DISABLE_ALARM = 0x10,
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GBTAMA6_ENABLE_ALARM = 0x11,
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};
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enum GBHuC3Register {
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GBHUC3_RTC_MINUTES_LO = 0x10,
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GBHUC3_RTC_MINUTES_MI = 0x11,
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GBHUC3_RTC_MINUTES_HI = 0x12,
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GBHUC3_RTC_DAYS_LO = 0x13,
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GBHUC3_RTC_DAYS_MI = 0x14,
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GBHUC3_RTC_DAYS_HI = 0x15,
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GBHUC3_RTC_ENABLE = 0x16,
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GBHUC3_SPEAKER_TONE = 0x26,
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GBHUC3_SPEAKER_ENABLE = 0x27,
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GBHUC3_ALARM_MINUTES_LO = 0x58,
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GBHUC3_ALARM_MINUTES_MI = 0x59,
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GBHUC3_ALARM_MINUTES_HI = 0x5A,
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GBHUC3_ALARM_DAYS_LO = 0x5B,
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GBHUC3_ALARM_DAYS_MI = 0x5C,
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GBHUC3_ALARM_DAYS_HI = 0x5D,
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GBHUC3_ALARM_TONE = 0x5E,
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GBHUC3_ALARM_ENABLE = 0x5F,
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};
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enum GBHuC3Mode {
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GBHUC3_MODE_SRAM_RO = 0x0,
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GBHUC3_MODE_SRAM_RW = 0xA,
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GBHUC3_MODE_IN = 0xB,
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GBHUC3_MODE_OUT = 0xC,
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GBHUC3_MODE_COMMIT = 0xD,
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};
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enum GBHuC3Command {
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GBHUC3_CMD_LATCH = 0x0,
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GBHUC3_CMD_SET_RTC = 0x1,
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GBHUC3_CMD_RO = 0x2,
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GBHUC3_CMD_TONE = 0xE,
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};
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enum GBSachenLockMode {
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GB_SACHEN_LOCKED_DMG = 0,
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GB_SACHEN_LOCKED_CGB,
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GB_SACHEN_UNLOCKED
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};
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struct GBMBC1State {
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int mode;
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int multicartStride;
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uint8_t bankLo;
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uint8_t bankHi;
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};
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struct GBMBC6State {
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bool flashBank0;
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bool flashBank1;
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};
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struct GBMBC7State {
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enum GBMBC7MachineState state;
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uint16_t sr;
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uint8_t address;
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bool writable;
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int srBits;
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uint8_t access;
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uint8_t latch;
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GBMBC7Field eeprom;
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};
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struct GBMMM01State {
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bool locked;
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int currentBank0;
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};
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struct GBPocketCamState {
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bool registersActive;
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uint8_t registers[0x36];
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};
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struct GBTAMA5State {
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uint8_t reg;
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bool disabled;
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uint8_t registers[GBTAMA5_MAX];
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uint8_t rtcTimerPage[GBTAMA6_RTC_MAX];
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uint8_t rtcAlarmPage[GBTAMA6_RTC_MAX];
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uint8_t rtcFreePage0[GBTAMA6_RTC_MAX];
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uint8_t rtcFreePage1[GBTAMA6_RTC_MAX];
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};
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struct GBHuC3State {
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uint8_t index;
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uint8_t value;
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uint8_t mode;
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uint8_t registers[256];
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};
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struct GBPKJDState {
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uint8_t reg[2];
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};
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struct GBNTOldState {
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bool swapped;
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uint8_t baseBank;
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uint8_t bankCount;
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bool rumble;
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};
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struct GBNTNewState {
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bool splitMode;
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};
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struct GBBBDState {
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int dataSwapMode;
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int bankSwapMode;
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};
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struct GBSachenState {
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enum GBSachenLockMode locked;
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int transition;
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uint8_t mask;
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uint8_t unmaskedBank;
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uint8_t baseBank;
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};
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struct GBSintaxState {
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uint8_t mode;
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uint8_t xorValues[4];
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uint8_t bankNo;
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uint8_t romBankXor;
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};
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union GBMBCState {
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struct GBMBC1State mbc1;
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struct GBMBC6State mbc6;
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struct GBMBC7State mbc7;
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struct GBMMM01State mmm01;
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struct GBPocketCamState pocketCam;
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struct GBTAMA5State tama5;
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struct GBHuC3State huc3;
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struct GBNTOldState ntOld;
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struct GBNTNewState ntNew;
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struct GBPKJDState pkjd;
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struct GBBBDState bbd;
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struct GBSachenState sachen;
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struct GBSintaxState sintax;
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};
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struct mRotationSource;
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struct GBMemory {
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uint8_t* rom;
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uint8_t* romBase;
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uint8_t* romBank;
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enum GBMemoryBankControllerType mbcType;
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GBMemoryBankControllerWrite mbcWrite;
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GBMemoryBankControllerRead mbcRead;
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union GBMBCState mbcState;
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int currentBank;
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int currentBank0;
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int currentBank1;
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uint8_t* romBank1;
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int currentSramBank1;
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uint8_t* sramBank1;
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int cartBusDecay;
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uint16_t cartBusPc;
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uint8_t cartBus;
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uint8_t* wram;
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uint8_t* wramBank;
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int wramCurrentBank;
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bool mbcReadBank0;
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bool mbcReadBank1;
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bool mbcReadHigh;
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bool mbcWriteHigh;
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bool sramAccess;
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bool directSramAccess;
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uint8_t* sram;
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uint8_t* sramBank;
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int sramCurrentBank;
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uint8_t io[GB_SIZE_IO];
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bool ime;
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uint8_t ie;
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uint8_t hram[GB_SIZE_HRAM];
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uint16_t dmaSource;
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uint16_t dmaDest;
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int dmaRemaining;
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uint16_t hdmaSource;
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uint16_t hdmaDest;
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int hdmaRemaining;
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bool isHdma;
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struct mTimingEvent dmaEvent;
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struct mTimingEvent hdmaEvent;
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size_t romSize;
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bool rtcAccess;
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int activeRtcReg;
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bool rtcLatched;
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uint8_t rtcRegs[5];
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time_t rtcLastLatch;
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struct mRTCSource* rtc;
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struct mRotationSource* rotation;
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struct mRumble* rumble;
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int32_t lastRumble;
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struct mImageSource* cam;
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};
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struct SM83Core;
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void GBMemoryInit(struct GB* gb);
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void GBMemoryDeinit(struct GB* gb);
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void GBMemoryReset(struct GB* gb);
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void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
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uint8_t GBLoad8(struct SM83Core* cpu, uint16_t address);
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void GBStore8(struct SM83Core* cpu, uint16_t address, int8_t value);
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int GBCurrentSegment(struct SM83Core* cpu, uint16_t address);
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uint8_t GBView8(struct SM83Core* cpu, uint16_t address, int segment);
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void GBMemoryDMA(struct GB* gb, uint16_t base);
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uint8_t GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
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void GBPatch8(struct SM83Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
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struct GBSerializedState;
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void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
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void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
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CXX_GUARD_END
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#endif
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