731 lines
17 KiB
C
731 lines
17 KiB
C
/* Copyright (c) 2013-2016 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#include <mgba/internal/gb/mbc.h>
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#include <mgba/core/interface.h>
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#include <mgba/internal/lr35902/lr35902.h>
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#include <mgba/internal/gb/gb.h>
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#include <mgba/internal/gb/memory.h>
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#include <mgba-util/vfs.h>
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mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
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static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
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UNUSED(gb);
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UNUSED(address);
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UNUSED(value);
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mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
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}
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static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
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static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
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static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
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static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
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static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
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static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
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static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
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void GBMBCSwitchBank(struct GB* gb, int bank) {
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size_t bankStart = bank * GB_SIZE_CART_BANK0;
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if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
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mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
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bankStart &= (gb->memory.romSize - 1);
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bank = bankStart / GB_SIZE_CART_BANK0;
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if (!bank) {
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++bank;
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}
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}
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gb->memory.romBank = &gb->memory.rom[bankStart];
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gb->memory.currentBank = bank;
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if (gb->cpu->pc < GB_BASE_VRAM) {
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gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
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}
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}
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static void _switchBank0(struct GB* gb, int bank) {
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size_t bankStart = bank * GB_SIZE_CART_BANK0 << gb->memory.mbcState.mbc1.multicartStride;
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if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
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mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
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bankStart &= (gb->memory.romSize - 1);
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}
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gb->memory.romBase = &gb->memory.rom[bankStart];
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if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
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gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
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}
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}
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static bool _isMulticart(const uint8_t* mem) {
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bool success = true;
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struct VFile* vf;
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vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
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success = success && GBIsROM(vf);
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vf->close(vf);
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vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
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success = success && GBIsROM(vf);
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vf->close(vf);
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return success;
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}
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void GBMBCSwitchSramBank(struct GB* gb, int bank) {
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size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
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GBResizeSram(gb, (bank + 1) * GB_SIZE_EXTERNAL_RAM);
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gb->memory.sramBank = &gb->memory.sram[bankStart];
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gb->memory.sramCurrentBank = bank;
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}
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void GBMBCInit(struct GB* gb) {
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const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
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if (gb->memory.rom) {
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switch (cart->ramSize) {
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case 0:
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gb->sramSize = 0;
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break;
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case 1:
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gb->sramSize = 0x800;
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break;
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default:
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case 2:
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gb->sramSize = 0x2000;
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break;
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case 3:
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gb->sramSize = 0x8000;
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break;
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}
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if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
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switch (cart->type) {
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case 0:
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case 8:
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case 9:
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gb->memory.mbcType = GB_MBC_NONE;
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break;
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case 1:
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case 2:
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case 3:
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gb->memory.mbcType = GB_MBC1;
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if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
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gb->memory.mbcState.mbc1.multicartStride = 4;
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} else {
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gb->memory.mbcState.mbc1.multicartStride = 5;
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}
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break;
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case 5:
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case 6:
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gb->memory.mbcType = GB_MBC2;
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break;
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case 0x0F:
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case 0x10:
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gb->memory.mbcType = GB_MBC3_RTC;
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break;
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case 0x11:
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case 0x12:
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case 0x13:
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gb->memory.mbcType = GB_MBC3;
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break;
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default:
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mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
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// Fall through
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case 0x19:
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case 0x1A:
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case 0x1B:
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gb->memory.mbcType = GB_MBC5;
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break;
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case 0x1C:
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case 0x1D:
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case 0x1E:
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gb->memory.mbcType = GB_MBC5_RUMBLE;
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break;
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case 0x20:
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gb->memory.mbcType = GB_MBC6;
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break;
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case 0x22:
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gb->memory.mbcType = GB_MBC7;
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break;
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case 0xFE:
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gb->memory.mbcType = GB_HuC3;
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break;
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}
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}
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} else {
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gb->memory.mbcType = GB_MBC_NONE;
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}
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switch (gb->memory.mbcType) {
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case GB_MBC_NONE:
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gb->memory.mbc = _GBMBCNone;
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break;
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case GB_MBC1:
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gb->memory.mbc = _GBMBC1;
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break;
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case GB_MBC2:
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gb->memory.mbc = _GBMBC2;
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gb->sramSize = 0x200;
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break;
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case GB_MBC3:
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gb->memory.mbc = _GBMBC3;
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break;
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default:
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mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
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// Fall through
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case GB_MBC5:
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gb->memory.mbc = _GBMBC5;
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break;
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case GB_MBC6:
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mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
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gb->memory.mbc = _GBMBC6;
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break;
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case GB_MBC7:
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gb->memory.mbc = _GBMBC7;
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gb->sramSize = GB_SIZE_EXTERNAL_RAM;
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break;
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case GB_MMM01:
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mLOG(GB_MBC, WARN, "unimplemented MBC: MMM01");
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gb->memory.mbc = _GBMBC1;
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break;
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case GB_HuC1:
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mLOG(GB_MBC, WARN, "unimplemented MBC: HuC-1");
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gb->memory.mbc = _GBMBC1;
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break;
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case GB_HuC3:
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gb->memory.mbc = _GBHuC3;
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break;
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case GB_MBC3_RTC:
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memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
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gb->memory.mbc = _GBMBC3;
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break;
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case GB_MBC5_RUMBLE:
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gb->memory.mbc = _GBMBC5;
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break;
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}
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GBResizeSram(gb, gb->sramSize);
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if (gb->memory.mbcType == GB_MBC3_RTC) {
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GBMBCRTCRead(gb);
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}
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}
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static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
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time_t t;
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if (rtc) {
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if (rtc->sample) {
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rtc->sample(rtc);
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}
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t = rtc->unixTime(rtc);
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} else {
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t = time(0);
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}
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time_t currentLatch = t;
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t -= *rtcLastLatch;
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*rtcLastLatch = currentLatch;
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int64_t diff;
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diff = rtcRegs[0] + t % 60;
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if (diff < 0) {
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diff += 60;
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t -= 60;
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}
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rtcRegs[0] = diff % 60;
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t /= 60;
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t += diff / 60;
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diff = rtcRegs[1] + t % 60;
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if (diff < 0) {
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diff += 60;
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t -= 60;
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}
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rtcRegs[1] = diff % 60;
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t /= 60;
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t += diff / 60;
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diff = rtcRegs[2] + t % 24;
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if (diff < 0) {
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diff += 24;
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t -= 24;
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}
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rtcRegs[2] = diff % 24;
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t /= 24;
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t += diff / 24;
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diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
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rtcRegs[3] = diff;
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rtcRegs[4] &= 0xFE;
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rtcRegs[4] |= (diff >> 8) & 1;
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if (diff & 0x200) {
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rtcRegs[4] |= 0x80;
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}
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}
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void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
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struct GBMemory* memory = &gb->memory;
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int bank = value & 0x1F;
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int stride = 1 << memory->mbcState.mbc1.multicartStride;
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switch (address >> 13) {
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case 0x0:
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switch (value) {
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case 0:
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memory->sramAccess = false;
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break;
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case 0xA:
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memory->sramAccess = true;
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GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
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break;
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default:
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// TODO
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mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
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break;
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}
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break;
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case 0x1:
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if (!bank) {
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++bank;
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}
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bank &= stride - 1;
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GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
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break;
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case 0x2:
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bank &= 3;
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if (memory->mbcState.mbc1.mode) {
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_switchBank0(gb, bank);
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GBMBCSwitchSramBank(gb, bank);
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}
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GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
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break;
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case 0x3:
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memory->mbcState.mbc1.mode = value & 1;
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if (memory->mbcState.mbc1.mode) {
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_switchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
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} else {
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_switchBank0(gb, 0);
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GBMBCSwitchSramBank(gb, 0);
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}
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break;
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default:
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// TODO
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mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
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break;
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}
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}
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void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
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struct GBMemory* memory = &gb->memory;
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int bank = value & 0xF;
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switch (address >> 13) {
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case 0x0:
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switch (value) {
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case 0:
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memory->sramAccess = false;
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break;
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case 0xA:
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memory->sramAccess = true;
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GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
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break;
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default:
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// TODO
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mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
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break;
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}
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break;
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case 0x1:
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if (!bank) {
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++bank;
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}
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GBMBCSwitchBank(gb, bank);
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break;
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default:
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// TODO
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mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
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break;
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}}
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void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
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struct GBMemory* memory = &gb->memory;
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int bank = value & 0x7F;
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switch (address >> 13) {
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case 0x0:
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switch (value) {
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case 0:
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memory->sramAccess = false;
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break;
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case 0xA:
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memory->sramAccess = true;
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GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
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break;
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default:
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// TODO
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mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
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break;
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}
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break;
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case 0x1:
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if (!bank) {
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++bank;
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}
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GBMBCSwitchBank(gb, bank);
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break;
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case 0x2:
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if (value < 4) {
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GBMBCSwitchSramBank(gb, value);
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memory->rtcAccess = false;
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} else if (value >= 8 && value <= 0xC) {
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memory->activeRtcReg = value - 8;
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memory->rtcAccess = true;
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}
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break;
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case 0x3:
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if (memory->rtcLatched && value == 0) {
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memory->rtcLatched = false;
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} else if (!memory->rtcLatched && value == 1) {
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_latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
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memory->rtcLatched = true;
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}
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break;
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}
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}
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void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
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struct GBMemory* memory = &gb->memory;
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int bank;
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switch (address >> 12) {
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case 0x0:
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case 0x1:
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switch (value) {
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case 0:
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memory->sramAccess = false;
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break;
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case 0xA:
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memory->sramAccess = true;
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GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
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break;
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default:
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// TODO
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mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
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break;
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}
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break;
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case 0x2:
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bank = (memory->currentBank & 0x100) | value;
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GBMBCSwitchBank(gb, bank);
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break;
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case 0x3:
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bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
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GBMBCSwitchBank(gb, bank);
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break;
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case 0x4:
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case 0x5:
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if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
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memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
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value &= ~8;
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}
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GBMBCSwitchSramBank(gb, value & 0xF);
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break;
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default:
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// TODO
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mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
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break;
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}
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}
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void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
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// TODO
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mLOG(GB_MBC, STUB, "MBC6 unimplemented");
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UNUSED(gb);
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UNUSED(address);
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UNUSED(value);
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}
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void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
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int bank = value & 0x7F;
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switch (address >> 13) {
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case 0x1:
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GBMBCSwitchBank(gb, bank);
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break;
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case 0x2:
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if (value < 0x10) {
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GBMBCSwitchSramBank(gb, value);
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}
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break;
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default:
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// TODO
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mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
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break;
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}
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}
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uint8_t GBMBC7Read(struct GBMemory* memory, uint16_t address) {
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struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
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switch (address & 0xF0) {
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case 0x00:
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case 0x10:
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case 0x60:
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case 0x70:
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return 0;
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case 0x20:
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if (memory->rotation && memory->rotation->readTiltX) {
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int32_t x = -memory->rotation->readTiltX(memory->rotation);
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x >>= 21;
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x += 2047;
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return x;
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}
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return 0xFF;
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case 0x30:
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if (memory->rotation && memory->rotation->readTiltX) {
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int32_t x = -memory->rotation->readTiltX(memory->rotation);
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x >>= 21;
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x += 2047;
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return x >> 8;
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}
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return 7;
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case 0x40:
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if (memory->rotation && memory->rotation->readTiltY) {
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int32_t y = -memory->rotation->readTiltY(memory->rotation);
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y >>= 21;
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y += 2047;
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return y;
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}
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return 0xFF;
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case 0x50:
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if (memory->rotation && memory->rotation->readTiltY) {
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int32_t y = -memory->rotation->readTiltY(memory->rotation);
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y >>= 21;
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y += 2047;
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return y >> 8;
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}
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return 7;
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case 0x80:
|
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return (mbc7->sr >> 16) & 1;
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default:
|
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return 0xFF;
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}
|
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}
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void GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
|
|
if ((address & 0xF0) != 0x80) {
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|
return;
|
|
}
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|
struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
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|
GBMBC7Field old = memory->mbcState.mbc7.field;
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|
mbc7->field = GBMBC7FieldClearIO(value);
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|
if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
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|
if (mbc7->state == GBMBC7_STATE_WRITE) {
|
|
if (mbc7->writable) {
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|
memory->sramBank[mbc7->address * 2] = mbc7->sr >> 8;
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|
memory->sramBank[mbc7->address * 2 + 1] = mbc7->sr;
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|
}
|
|
mbc7->sr = 0x1FFFF;
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|
mbc7->state = GBMBC7_STATE_NULL;
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|
} else {
|
|
mbc7->state = GBMBC7_STATE_IDLE;
|
|
}
|
|
}
|
|
if (!GBMBC7FieldIsSK(old) && GBMBC7FieldIsSK(value)) {
|
|
if (mbc7->state > GBMBC7_STATE_IDLE && mbc7->state != GBMBC7_STATE_READ) {
|
|
mbc7->sr <<= 1;
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|
mbc7->sr |= GBMBC7FieldGetIO(value);
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|
++mbc7->srBits;
|
|
}
|
|
switch (mbc7->state) {
|
|
case GBMBC7_STATE_IDLE:
|
|
if (GBMBC7FieldIsIO(value)) {
|
|
mbc7->state = GBMBC7_STATE_READ_COMMAND;
|
|
mbc7->srBits = 0;
|
|
mbc7->sr = 0;
|
|
}
|
|
break;
|
|
case GBMBC7_STATE_READ_COMMAND:
|
|
if (mbc7->srBits == 2) {
|
|
mbc7->state = GBMBC7_STATE_READ_ADDRESS;
|
|
mbc7->srBits = 0;
|
|
mbc7->command = mbc7->sr;
|
|
}
|
|
break;
|
|
case GBMBC7_STATE_READ_ADDRESS:
|
|
if (mbc7->srBits == 8) {
|
|
mbc7->state = GBMBC7_STATE_COMMAND_0 + mbc7->command;
|
|
mbc7->srBits = 0;
|
|
mbc7->address = mbc7->sr;
|
|
if (mbc7->state == GBMBC7_STATE_COMMAND_0) {
|
|
switch (mbc7->address >> 6) {
|
|
case 0:
|
|
mbc7->writable = false;
|
|
mbc7->state = GBMBC7_STATE_NULL;
|
|
break;
|
|
case 3:
|
|
mbc7->writable = true;
|
|
mbc7->state = GBMBC7_STATE_NULL;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
case GBMBC7_STATE_COMMAND_0:
|
|
if (mbc7->srBits == 16) {
|
|
switch (mbc7->address >> 6) {
|
|
case 0:
|
|
mbc7->writable = false;
|
|
mbc7->state = GBMBC7_STATE_NULL;
|
|
break;
|
|
case 1:
|
|
mbc7->state = GBMBC7_STATE_WRITE;
|
|
if (mbc7->writable) {
|
|
int i;
|
|
for (i = 0; i < 256; ++i) {
|
|
memory->sramBank[i * 2] = mbc7->sr >> 8;
|
|
memory->sramBank[i * 2 + 1] = mbc7->sr;
|
|
}
|
|
}
|
|
break;
|
|
case 2:
|
|
mbc7->state = GBMBC7_STATE_WRITE;
|
|
if (mbc7->writable) {
|
|
int i;
|
|
for (i = 0; i < 256; ++i) {
|
|
memory->sramBank[i * 2] = 0xFF;
|
|
memory->sramBank[i * 2 + 1] = 0xFF;
|
|
}
|
|
}
|
|
break;
|
|
case 3:
|
|
mbc7->writable = true;
|
|
mbc7->state = GBMBC7_STATE_NULL;
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case GBMBC7_STATE_COMMAND_SR_WRITE:
|
|
if (mbc7->srBits == 16) {
|
|
mbc7->srBits = 0;
|
|
mbc7->state = GBMBC7_STATE_WRITE;
|
|
}
|
|
break;
|
|
case GBMBC7_STATE_COMMAND_SR_READ:
|
|
if (mbc7->srBits == 1) {
|
|
mbc7->sr = memory->sramBank[mbc7->address * 2] << 8;
|
|
mbc7->sr |= memory->sramBank[mbc7->address * 2 + 1];
|
|
mbc7->srBits = 0;
|
|
mbc7->state = GBMBC7_STATE_READ;
|
|
}
|
|
break;
|
|
case GBMBC7_STATE_COMMAND_SR_FILL:
|
|
if (mbc7->srBits == 16) {
|
|
mbc7->sr = 0xFFFF;
|
|
mbc7->srBits = 0;
|
|
mbc7->state = GBMBC7_STATE_WRITE;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
} else if (GBMBC7FieldIsSK(old) && !GBMBC7FieldIsSK(value)) {
|
|
if (mbc7->state == GBMBC7_STATE_READ) {
|
|
mbc7->sr <<= 1;
|
|
++mbc7->srBits;
|
|
if (mbc7->srBits == 16) {
|
|
mbc7->srBits = 0;
|
|
mbc7->state = GBMBC7_STATE_NULL;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
|
|
struct GBMemory* memory = &gb->memory;
|
|
int bank = value & 0x3F;
|
|
if (address & 0x1FFF) {
|
|
mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
|
|
}
|
|
|
|
switch (address >> 13) {
|
|
case 0x0:
|
|
switch (value) {
|
|
case 0xA:
|
|
memory->sramAccess = true;
|
|
GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
|
|
break;
|
|
default:
|
|
memory->sramAccess = false;
|
|
break;
|
|
}
|
|
break;
|
|
case 0x1:
|
|
GBMBCSwitchBank(gb, bank);
|
|
break;
|
|
case 0x2:
|
|
GBMBCSwitchSramBank(gb, bank);
|
|
break;
|
|
default:
|
|
// TODO
|
|
mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void GBMBCRTCRead(struct GB* gb) {
|
|
struct GBMBCRTCSaveBuffer rtcBuffer;
|
|
struct VFile* vf = gb->sramVf;
|
|
if (!vf) {
|
|
return;
|
|
}
|
|
ssize_t end = vf->seek(vf, -sizeof(rtcBuffer), SEEK_END);
|
|
switch (end & 0x1FFF) {
|
|
case 0:
|
|
break;
|
|
case 0x1FFC:
|
|
vf->seek(vf, -sizeof(rtcBuffer) - 4, SEEK_END);
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
vf->read(vf, &rtcBuffer, sizeof(rtcBuffer));
|
|
|
|
LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
|
|
LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
|
|
LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
|
|
LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
|
|
LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
|
|
LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
|
|
}
|
|
|
|
void GBMBCRTCWrite(struct GB* gb) {
|
|
struct VFile* vf = gb->sramVf;
|
|
if (!vf) {
|
|
return;
|
|
}
|
|
|
|
uint8_t rtcRegs[5];
|
|
memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
|
|
time_t rtcLastLatch = gb->memory.rtcLastLatch;
|
|
_latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
|
|
|
|
struct GBMBCRTCSaveBuffer rtcBuffer;
|
|
STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
|
|
STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
|
|
STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
|
|
STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
|
|
STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
|
|
STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
|
|
STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
|
|
STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
|
|
STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
|
|
STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
|
|
STORE_64LE(rtcLastLatch, 0, &rtcBuffer.unixTime);
|
|
|
|
if (vf->size(vf) == gb->sramSize) {
|
|
// Writing past the end of the file can invalidate the file mapping
|
|
vf->unmap(vf, gb->memory.sram, gb->sramSize);
|
|
gb->memory.sram = NULL;
|
|
}
|
|
vf->seek(vf, gb->sramSize, SEEK_SET);
|
|
vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
|
|
if (!gb->memory.sram) {
|
|
gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
|
|
GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
|
|
}
|
|
}
|