183 lines
4.0 KiB
C
183 lines
4.0 KiB
C
/* Copyright (c) 2013-2016 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef GB_MEMORY_H
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#define GB_MEMORY_H
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#include <mgba-util/common.h>
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CXX_GUARD_START
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#include <mgba/core/log.h>
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#include <mgba/core/timing.h>
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#include <mgba/gb/interface.h>
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mLOG_DECLARE_CATEGORY(GB_MBC);
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mLOG_DECLARE_CATEGORY(GB_MEM);
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struct GB;
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enum {
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GB_BASE_CART_BANK0 = 0x0000,
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GB_BASE_CART_BANK1 = 0x4000,
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GB_BASE_VRAM = 0x8000,
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GB_BASE_EXTERNAL_RAM = 0xA000,
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GB_BASE_WORKING_RAM_BANK0 = 0xC000,
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GB_BASE_WORKING_RAM_BANK1 = 0xD000,
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GB_BASE_OAM = 0xFE00,
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GB_BASE_UNUSABLE = 0xFEA0,
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GB_BASE_IO = 0xFF00,
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GB_BASE_HRAM = 0xFF80,
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GB_BASE_IE = 0xFFFF
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};
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enum {
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GB_REGION_CART_BANK0 = 0x0,
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GB_REGION_CART_BANK1 = 0x4,
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GB_REGION_VRAM = 0x8,
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GB_REGION_EXTERNAL_RAM = 0xA,
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GB_REGION_WORKING_RAM_BANK0 = 0xC,
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GB_REGION_WORKING_RAM_BANK1 = 0xD,
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GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
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GB_REGION_OTHER = 0xF,
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};
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enum {
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GB_SIZE_CART_BANK0 = 0x4000,
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GB_SIZE_CART_MAX = 0x800000,
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GB_SIZE_VRAM = 0x4000,
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GB_SIZE_VRAM_BANK0 = 0x2000,
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GB_SIZE_EXTERNAL_RAM = 0x2000,
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GB_SIZE_WORKING_RAM = 0x8000,
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GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
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GB_SIZE_OAM = 0xA0,
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GB_SIZE_IO = 0x80,
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GB_SIZE_HRAM = 0x7F,
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};
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enum {
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GB_SRAM_DIRT_NEW = 1,
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GB_SRAM_DIRT_SEEN = 2
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};
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struct GBMemory;
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typedef void (*GBMemoryBankController)(struct GB*, uint16_t address, uint8_t value);
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DECL_BITFIELD(GBMBC7Field, uint8_t);
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DECL_BIT(GBMBC7Field, SK, 6);
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DECL_BIT(GBMBC7Field, CS, 7);
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DECL_BIT(GBMBC7Field, IO, 1);
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enum GBMBC7MachineState {
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GBMBC7_STATE_NULL = -1,
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GBMBC7_STATE_IDLE = 0,
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GBMBC7_STATE_READ_COMMAND = 1,
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GBMBC7_STATE_READ_ADDRESS = 2,
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GBMBC7_STATE_COMMAND_0 = 3,
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GBMBC7_STATE_COMMAND_SR_WRITE = 4,
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GBMBC7_STATE_COMMAND_SR_READ = 5,
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GBMBC7_STATE_COMMAND_SR_FILL = 6,
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GBMBC7_STATE_READ = 7,
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GBMBC7_STATE_WRITE = 8,
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};
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struct GBMBC1State {
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int mode;
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};
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struct GBMBC7State {
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enum GBMBC7MachineState state;
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uint32_t sr;
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uint8_t address;
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bool writable;
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int srBits;
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int command;
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GBMBC7Field field;
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};
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union GBMBCState {
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struct GBMBC1State mbc1;
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struct GBMBC7State mbc7;
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};
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struct mRotationSource;
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struct GBMemory {
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uint8_t* rom;
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uint8_t* romBase;
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uint8_t* romBank;
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enum GBMemoryBankControllerType mbcType;
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GBMemoryBankController mbc;
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union GBMBCState mbcState;
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int currentBank;
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uint8_t* wram;
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uint8_t* wramBank;
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int wramCurrentBank;
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bool sramAccess;
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uint8_t* sram;
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uint8_t* sramBank;
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int sramCurrentBank;
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uint8_t io[GB_SIZE_IO];
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bool ime;
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uint8_t ie;
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uint8_t hram[GB_SIZE_HRAM];
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uint16_t dmaSource;
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uint16_t dmaDest;
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int dmaRemaining;
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uint16_t hdmaSource;
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uint16_t hdmaDest;
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int hdmaRemaining;
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bool isHdma;
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struct mTimingEvent dmaEvent;
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struct mTimingEvent hdmaEvent;
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size_t romSize;
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bool rtcAccess;
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int activeRtcReg;
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bool rtcLatched;
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uint8_t rtcRegs[5];
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time_t rtcLastLatch;
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struct mRTCSource* rtc;
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struct mRotationSource* rotation;
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struct mRumble* rumble;
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};
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struct LR35902Core;
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void GBMemoryInit(struct GB* gb);
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void GBMemoryDeinit(struct GB* gb);
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void GBMemoryReset(struct GB* gb);
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void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
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uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
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void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
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int GBCurrentSegment(struct LR35902Core* cpu, uint16_t address);
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uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment);
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void GBMemoryDMA(struct GB* gb, uint16_t base);
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void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
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uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address);
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void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
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void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
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struct GBSerializedState;
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void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
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void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
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CXX_GUARD_END
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#endif
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