Last fix was wrong, this is correct
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517f455486
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@ -436,6 +436,7 @@ struct GB_gameboy_internal_s {
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bool dma_ppu_vram_conflict;
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uint16_t dma_ppu_vram_conflict_addr;
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uint8_t hdma_open_bus; /* Required to emulate HDMA reads from Exxx */
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bool allow_hdma_on_wake;
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)
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/* MBC */
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@ -360,6 +360,7 @@ static void enter_stop_mode(GB_gameboy_t *gb)
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gb->div_cycles = -4; // Emulate the CPU-side DIV-reset signal being held
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}
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gb->stopped = true;
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gb->allow_hdma_on_wake = (gb->io_registers[GB_IO_STAT] & 3);
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gb->oam_ppu_blocked = !gb->oam_read_blocked;
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gb->vram_ppu_blocked = !gb->vram_read_blocked;
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gb->cgb_palettes_ppu_blocked = !gb->cgb_palettes_blocked;
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@ -368,6 +369,9 @@ static void enter_stop_mode(GB_gameboy_t *gb)
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static void leave_stop_mode(GB_gameboy_t *gb)
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{
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gb->stopped = false;
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if (gb->hdma_on_hblank && (gb->io_registers[GB_IO_STAT] & 3) == 0 && gb->allow_hdma_on_wake) {
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gb->hdma_on = true;
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}
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// TODO: verify this
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gb->dma_cycles = 4;
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GB_dma_run(gb);
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@ -437,6 +441,7 @@ static void stop(GB_gameboy_t *gb, uint8_t opcode)
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GB_dma_run(gb);
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gb->halted = true;
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gb->just_halted = true;
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gb->allow_hdma_on_wake = (gb->io_registers[GB_IO_STAT] & 3);
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}
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else {
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gb->speed_switch_halt_countdown = 0;
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@ -1038,6 +1043,7 @@ static void halt(GB_gameboy_t *gb, uint8_t opcode)
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}
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else {
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gb->halted = true;
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gb->allow_hdma_on_wake = (gb->io_registers[GB_IO_STAT] & 3);
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}
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gb->just_halted = true;
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}
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@ -1631,6 +1637,9 @@ void GB_cpu_run(GB_gameboy_t *gb)
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/* Wake up from HALT mode without calling interrupt code. */
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if (gb->halted && !effective_ime && interrupt_queue) {
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gb->halted = false;
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if (gb->hdma_on_hblank && (gb->io_registers[GB_IO_STAT] & 3) == 0 && gb->allow_hdma_on_wake) {
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gb->hdma_on = true;
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}
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gb->dma_cycles = 4;
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GB_dma_run(gb);
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gb->speed_switch_halt_countdown = 0;
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@ -1639,6 +1648,9 @@ void GB_cpu_run(GB_gameboy_t *gb)
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/* Call interrupt */
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else if (effective_ime && interrupt_queue) {
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gb->halted = false;
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if (gb->hdma_on_hblank && (gb->io_registers[GB_IO_STAT] & 3) == 0 && gb->allow_hdma_on_wake) {
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gb->hdma_on = true;
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}
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// TODO: verify the timing!
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gb->dma_cycles = 4;
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GB_dma_run(gb);
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