Emulate PPU OAM reads while both DMA and GDMA are active
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@ -469,6 +469,9 @@ static inline uint8_t oam_read(GB_gameboy_t *gb, uint8_t addr)
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return 0xFF;
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}
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if (unlikely(gb->dma_current_dest <= 0xa0 && gb->dma_current_dest > 0)) { // TODO: what happens in the last and first M cycles?
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if (gb->hdma_in_progress) {
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return GB_read_oam(gb, (gb->hdma_current_src & ~1) | (addr & 1));
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}
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return gb->oam[((gb->dma_current_dest - 1 + (gb->halted || gb->stopped)) & ~1) | (addr & 1)];
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}
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return gb->oam[addr];
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@ -473,7 +473,7 @@ static inline void sync_ppu_if_needed(GB_gameboy_t *gb, uint8_t register_accesse
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}
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}
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static uint8_t read_oam(GB_gameboy_t *gb, uint8_t addr)
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internal uint8_t GB_read_oam(GB_gameboy_t *gb, uint8_t addr)
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{
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if (addr < 0xa0) {
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return gb->oam[addr];
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@ -588,7 +588,7 @@ static uint8_t read_high_memory(GB_gameboy_t *gb, uint16_t addr)
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return 0xff;
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}
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return read_oam(gb, addr);
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return GB_read_oam(gb, addr);
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}
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if (addr < 0xFF80) {
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@ -16,6 +16,7 @@ internal void GB_dma_run(GB_gameboy_t *gb);
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internal bool GB_is_dma_active(GB_gameboy_t *gb);
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internal void GB_hdma_run(GB_gameboy_t *gb);
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internal void GB_trigger_oam_bug(GB_gameboy_t *gb, uint16_t address);
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internal uint8_t GB_read_oam(GB_gameboy_t *gb, uint8_t addr);
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#endif
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#endif /* memory_h */
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