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Fixed a regression with STAT blocking.

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This commit is contained in:
Lior Halphon 2018-06-02 04:00:10 +03:00
parent 80c92daacd
commit 7003e31b7e
1 changed files with 8 additions and 2 deletions
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10
Core/display.c
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@ -535,6 +535,10 @@ static void advance_fetcher_state_machine(GB_gameboy_t *gb)
gb->fetcher_state &= 7; gb->fetcher_state &= 7;
} }
/*
TODO: It seems that the STAT register's mode bits are always "late" by 4 T-cycles.
The PPU logic can be greatly simplified if that delay is simply emulated.
*/
void GB_display_run(GB_gameboy_t *gb, uint8_t cycles) void GB_display_run(GB_gameboy_t *gb, uint8_t cycles)
{ {
GB_object_t *objects = (GB_object_t *) &gb->oam; GB_object_t *objects = (GB_object_t *) &gb->oam;
@ -634,7 +638,7 @@ void GB_display_run(GB_gameboy_t *gb, uint8_t cycles)
/* Mode 0 is shorter in the very first line */ /* Mode 0 is shorter in the very first line */
GB_SLEEP(gb, display, 5, LINE_LENGTH - gb->cycles_for_line - 8); GB_SLEEP(gb, display, 5, LINE_LENGTH - gb->cycles_for_line - 8);
gb->mode_0_interrupt_disable = true; gb->mode_0_interrupt_disable = !(gb->io_registers[GB_IO_STAT] & 0x20);
gb->current_line = 1; gb->current_line = 1;
while (true) { while (true) {
/* Lines 0 - 143 */ /* Lines 0 - 143 */
@ -824,7 +828,9 @@ void GB_display_run(GB_gameboy_t *gb, uint8_t cycles)
gb->hdma_starting = true; gb->hdma_starting = true;
} }
GB_SLEEP(gb, display, 11, LINE_LENGTH - gb->cycles_for_line); GB_SLEEP(gb, display, 11, LINE_LENGTH - gb->cycles_for_line);
gb->mode_0_interrupt_disable = true; /* Todo: The last cycle of move 0 can't trigger an interrupt... unless OAM interrupt is requested?
This doesn't make too much sense. */
gb->mode_0_interrupt_disable = !(gb->io_registers[GB_IO_STAT] & 0x20);
} }
/* Lines 144 - 152 */ /* Lines 144 - 152 */