Correctly emulate speed switch timing
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c74b39e712
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@ -403,6 +403,7 @@ struct GB_gameboy_internal_s {
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uint8_t tima_reload_state; /* After TIMA overflows, it becomes 0 for 4 cycles before actually reloading. */
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uint8_t tima_reload_state; /* After TIMA overflows, it becomes 0 for 4 cycles before actually reloading. */
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uint16_t serial_cycles;
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uint16_t serial_cycles;
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uint16_t serial_length;
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uint16_t serial_length;
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uint8_t double_speed_alignment;
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);
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);
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/* APU */
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/* APU */
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@ -211,14 +211,27 @@ static void nop(GB_gameboy_t *gb, uint8_t opcode)
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static void stop(GB_gameboy_t *gb, uint8_t opcode)
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static void stop(GB_gameboy_t *gb, uint8_t opcode)
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{
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{
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if (gb->io_registers[GB_IO_KEY1] & 0x1) {
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if (gb->io_registers[GB_IO_KEY1] & 0x1) {
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/* Make sure we don't leave display_cycles not divisble by 8 in single speed mode */
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flush_pending_cycles(gb);
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if (gb->display_cycles % 8 == 4) {
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bool needs_alignment = false;
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cycle_no_access(gb);
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GB_advance_cycles(gb, 0x4);
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/* Make sure we keep the CPU ticks aligned correctly when returning from double speed mode */
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if (gb->double_speed_alignment & 7) {
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GB_advance_cycles(gb, 0x4);
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needs_alignment = true;
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}
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}
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/* Todo: the switch is not instant. We should emulate this. */
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gb->cgb_double_speed ^= true;
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gb->cgb_double_speed ^= true;
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gb->io_registers[GB_IO_KEY1] = 0;
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gb->io_registers[GB_IO_KEY1] = 0;
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for (unsigned i = 0x800; i--;) {
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GB_advance_cycles(gb, 0x40);
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}
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if (!needs_alignment) {
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GB_advance_cycles(gb, 0x4);
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}
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}
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}
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else {
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else {
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gb->stopped = true;
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gb->stopped = true;
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@ -193,6 +193,7 @@ void GB_advance_cycles(GB_gameboy_t *gb, uint8_t cycles)
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}
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}
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// Not affected by speed boost
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// Not affected by speed boost
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gb->double_speed_alignment += cycles;
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gb->hdma_cycles += cycles;
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gb->hdma_cycles += cycles;
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gb->apu_output.sample_cycles += cycles;
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gb->apu_output.sample_cycles += cycles;
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gb->cycles_since_ir_change += cycles;
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gb->cycles_since_ir_change += cycles;
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