Fix CGB timings
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3e5e17d1a3
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c11af7ea26
@ -434,7 +434,9 @@ void GB_display_run(GB_gameboy_t *gb, uint8_t cycles)
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return;
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return;
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}
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}
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GB_SLEEP(gb, display, 23, 1);
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if (!gb->is_cgb) {
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GB_SLEEP(gb, display, 23, 1);
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}
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/* Handle the very first line 0 */
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/* Handle the very first line 0 */
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gb->current_line = 0;
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gb->current_line = 0;
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@ -464,8 +466,6 @@ void GB_display_run(GB_gameboy_t *gb, uint8_t cycles)
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gb->cycles_for_line += MODE3_LENGTH + (gb->io_registers[GB_IO_SCX] & 7) - 2;
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gb->cycles_for_line += MODE3_LENGTH + (gb->io_registers[GB_IO_SCX] & 7) - 2;
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GB_SLEEP(gb, display, 3, MODE3_LENGTH + (gb->io_registers[GB_IO_SCX] & 7) - 2);
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GB_SLEEP(gb, display, 3, MODE3_LENGTH + (gb->io_registers[GB_IO_SCX] & 7) - 2);
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if (!gb->cgb_double_speed) {
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if (!gb->cgb_double_speed) {
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gb->io_registers[GB_IO_STAT] &= ~3;
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gb->io_registers[GB_IO_STAT] &= ~3;
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gb->oam_read_blocked = false;
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gb->oam_read_blocked = false;
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@ -676,14 +676,22 @@ void GB_display_run(GB_gameboy_t *gb, uint8_t cycles)
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gb->cycles_for_line++;
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gb->cycles_for_line++;
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GB_SLEEP(gb, display, 21, 1);
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GB_SLEEP(gb, display, 21, 1);
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}
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}
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if (!gb->cgb_double_speed) {
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gb->io_registers[GB_IO_STAT] &= ~3;
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gb->oam_read_blocked = false;
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gb->vram_read_blocked = false;
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gb->oam_write_blocked = false;
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gb->vram_write_blocked = false;
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}
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gb->cycles_for_line++;
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GB_SLEEP(gb, display, 22, 1);
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gb->io_registers[GB_IO_STAT] &= ~3;
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gb->io_registers[GB_IO_STAT] &= ~3;
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gb->oam_read_blocked = false;
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gb->oam_read_blocked = false;
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gb->vram_read_blocked = false;
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gb->vram_read_blocked = false;
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gb->oam_write_blocked = false;
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gb->oam_write_blocked = false;
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gb->vram_write_blocked = false;
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gb->vram_write_blocked = false;
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gb->cycles_for_line++;
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GB_SLEEP(gb, display, 22, 1);
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GB_STAT_update(gb);
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GB_STAT_update(gb);
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/* Todo: Measure this value */
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/* Todo: Measure this value */
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@ -153,6 +153,13 @@ static void GB_timers_run(GB_gameboy_t *gb, uint8_t cycles)
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void GB_advance_cycles(GB_gameboy_t *gb, uint8_t cycles)
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void GB_advance_cycles(GB_gameboy_t *gb, uint8_t cycles)
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{
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{
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/* It appears that on the CGB, write timing is a bit different then on the DMG, effectively
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making writes 1 T-cycle late when compared to the DMG. */
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if (gb->is_cgb) {
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cycles = (cycles + 1) & ~3;
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if (cycles == 0) return;
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}
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// Affected by speed boost
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// Affected by speed boost
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gb->dma_cycles += cycles;
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gb->dma_cycles += cycles;
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@ -180,12 +187,6 @@ void GB_advance_cycles(GB_gameboy_t *gb, uint8_t cycles)
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if (!gb->cgb_double_speed) {
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if (!gb->cgb_double_speed) {
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cycles <<= 1;
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cycles <<= 1;
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if ((cycles & 6) == 2) {
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cycles--;
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}
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else if ((cycles & 6) == 6) {
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cycles++;
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}
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}
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}
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// Not affected by speed boost
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// Not affected by speed boost
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