The STAT bug does not occur during the glitched mode 0
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@ -238,6 +238,7 @@ static void trigger_oam_interrupt(GB_gameboy_t *gb)
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}
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}
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}
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}
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/* Todo: A proper test ROM of cases where both the PPU and the CPU write to IF in the same M-cycle is needed. */
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void GB_STAT_update(GB_gameboy_t *gb)
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void GB_STAT_update(GB_gameboy_t *gb)
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{
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{
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if (!(gb->io_registers[GB_IO_LCDC] & 0x80)) return;
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if (!(gb->io_registers[GB_IO_LCDC] & 0x80)) return;
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@ -636,7 +636,7 @@ static void write_high_memory(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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case GB_IO_STAT:
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case GB_IO_STAT:
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/* A DMG bug: http://www.devrs.com/gb/files/faqs.html#GBBugs */
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/* A DMG bug: http://www.devrs.com/gb/files/faqs.html#GBBugs */
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if (!gb->is_cgb && !gb->stat_interrupt_line &&
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if (!gb->is_cgb && !gb->stat_interrupt_line && !gb->is_first_line_mode2 &&
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(gb->io_registers[GB_IO_STAT] & 0x3) < 2 && (gb->io_registers[GB_IO_LCDC] & 0x80)) {
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(gb->io_registers[GB_IO_STAT] & 0x3) < 2 && (gb->io_registers[GB_IO_LCDC] & 0x80)) {
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gb->io_registers[GB_IO_IF] |= 2;
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gb->io_registers[GB_IO_IF] |= 2;
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}
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}
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