Commit Graph

1600 Commits

Author SHA1 Message Date
Lior Halphon
742c9e95d3 Updated previous timing improvements to correctly implement double speed behavior 2017-09-08 23:46:38 +03:00
Lior Halphon
e5d354e896 Refined SCX’s effects on PPU timing 2017-09-08 23:02:24 +03:00
Lior Halphon
0f1fa3176f Refinements to LCD timing (breaks vblank_stat_intr-GS for now) 2017-09-08 12:59:57 +03:00
Lior Halphon
0f643e01b7 Removing the delayed interrupt mechanism, research is not complete enough for implementation 2017-09-08 12:58:35 +03:00
Lior Halphon
ba0e66a5b7 Merge branch 'master' into new_apu 2017-09-04 18:41:13 +03:00
Lior Halphon
72d26c7046 Fixed obscure timer behavior, fixed regression in rapid_toggle.gb. 2017-09-04 18:40:43 +03:00
Lior Halphon
9bde98dede SCY latching is now correctly emulated, rendering mode timing refined. 2017-09-04 15:45:18 +03:00
Lior Halphon
a1a13c61bf On CGB, the VBlank and STAT interrupts are “delayed” by one T-cycle (relative to IF) since they’re not aligned to a T-Cycle 2017-09-03 00:41:52 +03:00
Lior Halphon
0532d2a159 A test ROM I wrote seems to contradicts some of AntonioND’s findings regrading PPU timing in CGB mode. CGB mode now behaves like DMG mode until I figure out what caused the difference. 2017-09-02 23:51:02 +03:00
Lior Halphon
9b490396bb Fixed timing when turning the LCD display on during double speed mode 2017-09-02 23:26:45 +03:00
Lior Halphon
54eb51d8db Refined timer interrupt timing 2017-09-02 22:08:20 +03:00
Lior Halphon
e7d5cdbb42 Merge branch 'master' into new_apu 2017-08-20 01:37:33 +03:00
Lior Halphon
cbbaf2ee84 Refined Window behavior once more, Fixes #12 (While not breaking Donkey Kong or 007) 2017-08-20 01:34:12 +03:00
Lior Halphon
62878fdc7a More accurate div-event handling 2017-08-15 22:27:15 +03:00
Lior Halphon
8d011ca4b9 Accuracy improvements (Sweep) 2017-08-15 22:05:20 +03:00
Lior Halphon
5d84ee250e Added Cocoa GUI for the High-Pass filter selection 2017-08-15 21:59:53 +03:00
Lior Halphon
d04aaddcbd Added highpass filter 2017-08-15 21:59:11 +03:00
Lior Halphon
ca59aca4a6 Fixed a bug where writing to NR52 affected channels 1 and 2’s duty pattern in DMG mode. Fixed NR43 being written to NR44 as well. 2017-08-13 20:26:35 +03:00
Lior Halphon
36943866e2 Better click prevention 2017-08-12 23:35:18 +03:00
Lior Halphon
d43daed6a6 Merge branch 'master' into new_apu 2017-08-12 21:43:09 +03:00
Lior Halphon
7df4e56454 KEY1 is only writable in CGB mode; screen should be black is LCD is on while in stop mode. 2017-08-12 21:42:47 +03:00
Lior Halphon
dba7370d6d Turns out APU signal is inverted. This fixes Perfect Dark’s audio. 2017-08-12 20:47:55 +03:00
Lior Halphon
688991f57f The volume envelopes and length controls are handled in different phases of the div-divider 2017-08-12 20:17:20 +03:00
Lior Halphon
4b8be255ce Fixed some channel 4 delays, documented a not currently emulated timing quirk. 2017-08-12 19:50:39 +03:00
Lior Halphon
066efab985 In DMG mode, the length registers are not affected by turning the APU on and off. Why? Why not! 2017-08-11 22:23:03 +03:00
Lior Halphon
0e22ad8eb1 Noise channel support 2017-08-11 17:57:08 +03:00
Lior Halphon
1a8bcd314d Accuracy improvements to sweeping (Still not complete though, more research needed) 2017-08-10 19:42:23 +03:00
Lior Halphon
ab5611119a Accuracy improvements, especially to the length control 2017-08-02 21:14:23 +03:00
Lior Halphon
d65c2247e5 Added channel 1 and 2, fixed accuracy issues with channel 3 2017-07-27 23:11:33 +03:00
Lior Halphon
2936f7fa57 Fixed channel 3 counter behavior, verified with new tests. The DIV register ticks the APU at 512Hz. 2017-07-22 19:51:11 +03:00
Lior Halphon
a19ee1e5e0 2MHz audio downscaling support. Implemented NR50 and NR51. 2017-07-21 23:17:48 +03:00
Lior Halphon
baccf336d7 Complete rewrite of the APU. Channel 3 is complete and passes all the relevant tests from blargg’s suite, as well as PCM34-based tests. Actual sound output is basic and limited, though. 2017-07-21 19:06:55 +03:00
Lior Halphon
c0a8a570e8 Merge pull request #11 from nattthebear/master
Fix compilation in GCC 4.6.4
2017-07-17 12:22:52 +03:00
nattthebear
eb7492c6c6 Fix undefined behavior (sequence point modification). GCC 4.6.4 compiles the code incorrectly without this fix. 2017-07-16 21:08:07 -04:00
Lior Halphon
efc11783c7 Updated SameBoy’s “score” on mooneye-gb’s tests 2017-06-23 18:04:51 +03:00
Lior Halphon
c4ccbd5cce Improved serial interrupt timing, fixes boot_sclk_align. 2017-06-23 17:58:04 +03:00
Lior Halphon
623f92378d Added --boot option to the automatic tester to specify the boot ROM, better support for automatic testing of the mooneye-GB tests 2017-06-21 23:25:39 +03:00
Lior Halphon
c59272d46d Misc minor fixes, fixes several Mooneye-GB tests 2017-06-21 20:39:23 +03:00
Lior Halphon
efbc385417 Forgot to amend the last commit, it was broken. 2017-06-21 01:07:11 +03:00
Lior Halphon
aefca34b39 Improved MBC1 emulation. Fixed incorrect error messages. 2017-06-19 19:46:09 +03:00
Lior Halphon
abf7efcc5a Fixed lcdon_write_timing. 2017-06-18 21:27:07 +03:00
Lior Halphon
86c9f9d89d Updated SameBoy to pass Mooneye-GB’s lcdon_timing test (on a DMG), as well as refined related CBG behaviors. 2017-06-17 22:17:58 +03:00
Lior Halphon
bbd2ca8ddf Fixed Linux compilation 2017-06-16 01:25:39 +03:00
Lior Halphon
babcc0a7dc Added API to load/save states from RAM 2017-06-14 00:23:34 +03:00
Lior Halphon
204e22657b The CGB boot ROM will now not finish if the user is still selecting palettes 2017-06-09 19:52:40 +03:00
Lior Halphon
144d0348dd Loading a save state creating during the effect of the previous MBC RAM bug will now attempt to fix the (broken) save state. 2017-06-08 23:26:04 +03:00
Lior Halphon
c650337928 Fixed a bug where MBC RAM was no longer accessible after using the GB_reset functions 2017-06-08 22:48:23 +03:00
Lior Halphon
a9475fbdf4 Refined the behavior of the last fix on a DMG. 2017-06-03 20:06:52 +03:00
Lior Halphon
65b0dcb2c5 Fixed a bug where SameBoy freeze for a moment after leaving turbo mode 2017-06-03 17:02:12 +03:00
Lior Halphon
d72807dd67 Implemented LCD first-frame-skip behavior, fixes a visual glitch in Pokémon Pinball 2017-06-03 16:42:42 +03:00