Max/SameBoy
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55 Commits

Author SHA1 Message Date
Lior Halphon
713dc02e46 A bit tacky, but T-cycle accurate emulation of LYC write conflicts on the CGB. Only single speed mode verified. Closes #54 2018-05-11 12:38:55 +03:00
Lior Halphon
af3554c1d1 More accurate emulation of the LYC register and interrupt. (Still not perfect on a CGB) 2018-04-27 13:40:39 +03:00
Lior Halphon
be9df4d658 Added mechanism to handle MMIO read/write conflicts. Fixes #65 2018-04-14 17:57:00 +03:00
Lior Halphon
2c6f7906c5 Make multi-byte opcodes trigger the OAM bug when they increase PC 2018-04-14 15:32:55 +03:00
Lior Halphon
84aa06aba5 Clean up OAM bug code 2018-04-14 13:35:16 +03:00
Lior Halphon
d667d87bbe Refactor CPU code so handling access conflicts is possible 2018-04-14 13:25:55 +03:00
Lior Halphon
f1ec42d4ba H/GDMA was 4 times faster than it should have been. Made it also more accurate. Fixes #56 2018-04-13 14:41:39 +03:00
Lior Halphon
a9fbbd3894 Merge branch 'master' of https://github.com/LIJI32/SameBoy 2018-03-29 21:07:04 +03:00
Lior Halphon
e380a00b67 Fixed another timing regression with the CB opcodes 2018-03-29 21:06:53 +03:00
Kyle Swanson
7ffe132e79 fix typo 2018-03-28 21:38:48 -07:00
Lior Halphon
f5493e023d Fixed a timing regression in the CB opcodes 2018-03-27 20:21:24 +03:00
Lior Halphon
7543461c24 Increasing PC in OAM triggers the OAM bug 2018-03-27 16:36:39 +03:00
Lior Halphon
4986930511 Mostly complete emulation of the OAM bug. Passes oam_bug-2. 2018-03-27 15:46:00 +03:00
Lior Halphon
9093f22293 More accurate emulation of the OAM bug 2018-03-24 14:46:51 +03:00
Lior Halphon
d343152fca Basic emulation of the OAM bug 2018-03-24 00:32:19 +03:00
Lior Halphon
3e5e17d1a3 Fixed CB [hl] opcodes timings 2018-03-23 12:35:37 +03:00
Lior Halphon
3883b7d86a Merge branch 'master' into timing 
# Conflicts:
#	Core/display.c
#	Core/z80_cpu.c
 2018-03-19 23:46:33 +02:00
Lior Halphon
b50c97f4a7 Prevent starting HDMA in the middle of an instruction, making both the CPU and DMA access memory at the same time. Closes #47 2018-03-19 20:01:31 +02:00
Lior Halphon
0dc30f081a CGB halt interrupt timing 2018-03-17 23:21:14 +02:00
Lior Halphon
544ca2be4c Changing the timings of memory writes so they’re not effectively one T-cycle late. This screws up APU’s cycle accuracy for now. 2018-03-05 21:17:37 +02:00
Lior Halphon
b702d56547 Merge branch 'master' into timing 
# Conflicts:
#	Core/display.c
#	Core/z80_cpu.c
 2018-03-01 21:22:33 +02:00
Lior Halphon
90a943d05a Emulate an HDMA quirk required to properly emulate Aevilia 2018-02-25 22:32:41 +02:00
Lior Halphon
ef670986c6 Rewrote PPU (currently only emulates DMG correctly) to use the new timing mechanism. Removed “future interrupts” (No longer required because SameBoy is now T-cycle based) 2018-02-25 00:48:45 +02:00
Lior Halphon
42ab746a66 Starting to remove the delayed interrupts hack – done for timer interrupt, broken for display interrupts 2018-02-23 15:33:44 +02:00
Lior Halphon
5974092c94 Bugfix 2018-02-20 23:04:35 +02:00
Lior Halphon
19c382c9e0 Fixed ei_sequence test 2017-12-03 21:07:34 +02:00
Lior Halphon
be038dc8e7 Refinement to the last fix 2017-09-20 03:08:54 +03:00
Lior Halphon
57e7782ac4 Interrupt servicing is now more accurate. Fixes mooneye-gb’s ie_push (all models) and Pinball Deluxe (!!!) for CGB mode 2017-09-20 02:49:45 +03:00
Lior Halphon
14f267b4fa Another whoops 2017-09-09 19:31:05 +03:00
Lior Halphon
1e90400916 Reimplemented delayed/future interrupts, currently correct only for CGB. 2017-09-09 13:32:12 +03:00
Lior Halphon
0f643e01b7 Removing the delayed interrupt mechanism, research is not complete enough for implementation 2017-09-08 12:58:35 +03:00
Lior Halphon
54eb51d8db Refined timer interrupt timing 2017-09-02 22:08:20 +03:00
nattthebear
eb7492c6c6 Fix undefined behavior (sequence point modification). GCC 4.6.4 compiles the code incorrectly without this fix. 2017-07-16 21:08:07 -04:00
Lior Halphon
a925ef130d Stabilizing API: New joypad, debugger and reset APIs; internal APIs and direct struct access are no longer available without defining GB_INTERNAL. The SDL port uses the new “public” APIs, as well as most of the non-debug Cocoa code. 2017-04-17 20:16:17 +03:00
Lior Halphon
399e88d5fe STAT timing and LCD interrupts rewritten, should be more accurate. 2017-02-19 02:22:50 +02:00
Lior Halphon
74d00b84b7 Treat STOP as a 2-byte instruction 2017-02-17 00:21:02 +02:00
Lior Halphon
3fbc2c5716 DI should not be delayed. 2017-02-15 19:04:53 +02:00
Lior Halphon
2d51d13479 Various optimizations 2016-10-22 02:18:29 +03:00
Lior Halphon
0991705379 Refined HALT bug behavior, fixed Robocop 2016-09-22 01:51:09 +03:00
Lior Halphon
6f2b36cacb The HALT bug also happens on CGBs, regardless of DMG mode. 2016-09-20 22:59:25 +03:00
Lior Halphon
f049284324 Emulate the HALT bug on a DMG 2016-09-20 01:22:21 +03:00
Lior Halphon
1a3a96762b CPU cleanup 2016-09-18 23:50:04 +03:00
Lior Halphon
f4c5cf20bc Cleanup of ret_cc 2016-09-16 13:27:32 +03:00
Lior Halphon
43be91f032 Slightly more readable code. 2016-09-13 01:20:18 +03:00
Lior Halphon
a746c726ee Added basic automatic ROM tester 2016-09-03 03:39:32 +03:00
Lior Halphon
806d0775a4 Added backtrace command to debugger 2016-08-09 22:48:53 +03:00
Lior Halphon
e95d2c4abe Fixed DI instruction on CGB 2016-08-06 17:16:38 +03:00
Lior Halphon
4a50000e83 Corrected timing for many instructions 2016-08-06 14:00:35 +03:00
Lior Halphon
d098458ee4 Major improvements to accuracy: Fixed instruction timing, DMA timing, and IO reg masking. Passes most of mooneye-gb acceptance tests. 2016-08-05 16:36:38 +03:00
Lior Halphon
aa6438fa06 Async debugger commands 2016-07-18 00:46:45 +03:00