2016-06-18 17:29:11 +00:00
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#ifndef GB_h
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#define GB_h
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2016-03-30 20:07:55 +00:00
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#include <stdbool.h>
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#include <stdint.h>
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#include <time.h>
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2017-04-17 17:16:17 +00:00
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#include "gb_struct_def.h"
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2017-06-13 21:23:34 +00:00
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#include "save_state.h"
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2016-03-30 20:07:55 +00:00
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2017-04-17 17:16:17 +00:00
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#include "apu.h"
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#include "camera.h"
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#include "debugger.h"
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#include "display.h"
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#include "joypad.h"
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#include "mbc.h"
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2017-10-12 16:42:30 +00:00
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#include "memory.h"
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2017-04-17 17:16:17 +00:00
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#include "printer.h"
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#include "timing.h"
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2018-02-10 12:42:14 +00:00
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#include "rewind.h"
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2017-04-17 17:16:17 +00:00
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#include "z80_cpu.h"
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#include "symbol_hash.h"
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2016-06-11 11:52:09 +00:00
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2017-09-22 21:25:21 +00:00
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#define GB_STRUCT_VERSION 12
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2016-03-30 20:07:55 +00:00
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enum {
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GB_REGISTER_AF,
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GB_REGISTER_BC,
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GB_REGISTER_DE,
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GB_REGISTER_HL,
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GB_REGISTER_SP,
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GB_REGISTERS_16_BIT /* Count */
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};
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/* Todo: Actually use these! */
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enum {
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GB_CARRY_FLAG = 16,
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GB_HALF_CARRY_FLAG = 32,
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GB_SUBSTRACT_FLAG = 64,
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GB_ZERO_FLAG = 128,
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};
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2016-07-20 22:03:13 +00:00
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#define GB_MAX_IR_QUEUE 256
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2016-03-30 20:07:55 +00:00
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enum {
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/* Joypad and Serial */
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GB_IO_JOYP = 0x00, // Joypad (R/W)
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GB_IO_SB = 0x01, // Serial transfer data (R/W)
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GB_IO_SC = 0x02, // Serial Transfer Control (R/W)
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/* Missing */
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/* Timers */
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GB_IO_DIV = 0x04, // Divider Register (R/W)
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GB_IO_TIMA = 0x05, // Timer counter (R/W)
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GB_IO_TMA = 0x06, // Timer Modulo (R/W)
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GB_IO_TAC = 0x07, // Timer Control (R/W)
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/* Missing */
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GB_IO_IF = 0x0f, // Interrupt Flag (R/W)
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/* Sound */
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GB_IO_NR10 = 0x10, // Channel 1 Sweep register (R/W)
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GB_IO_NR11 = 0x11, // Channel 1 Sound length/Wave pattern duty (R/W)
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GB_IO_NR12 = 0x12, // Channel 1 Volume Envelope (R/W)
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GB_IO_NR13 = 0x13, // Channel 1 Frequency lo (Write Only)
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GB_IO_NR14 = 0x14, // Channel 1 Frequency hi (R/W)
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2017-07-27 20:11:33 +00:00
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/* NR20 does not exist */
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2016-03-30 20:07:55 +00:00
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GB_IO_NR21 = 0x16, // Channel 2 Sound Length/Wave Pattern Duty (R/W)
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GB_IO_NR22 = 0x17, // Channel 2 Volume Envelope (R/W)
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GB_IO_NR23 = 0x18, // Channel 2 Frequency lo data (W)
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GB_IO_NR24 = 0x19, // Channel 2 Frequency hi data (R/W)
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GB_IO_NR30 = 0x1a, // Channel 3 Sound on/off (R/W)
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GB_IO_NR31 = 0x1b, // Channel 3 Sound Length
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GB_IO_NR32 = 0x1c, // Channel 3 Select output level (R/W)
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GB_IO_NR33 = 0x1d, // Channel 3 Frequency's lower data (W)
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GB_IO_NR34 = 0x1e, // Channel 3 Frequency's higher data (R/W)
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2017-07-27 20:11:33 +00:00
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/* NR40 does not exist */
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2016-03-30 20:07:55 +00:00
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GB_IO_NR41 = 0x20, // Channel 4 Sound Length (R/W)
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GB_IO_NR42 = 0x21, // Channel 4 Volume Envelope (R/W)
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GB_IO_NR43 = 0x22, // Channel 4 Polynomial Counter (R/W)
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GB_IO_NR44 = 0x23, // Channel 4 Counter/consecutive, Inital (R/W)
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GB_IO_NR50 = 0x24, // Channel control / ON-OFF / Volume (R/W)
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GB_IO_NR51 = 0x25, // Selection of Sound output terminal (R/W)
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GB_IO_NR52 = 0x26, // Sound on/off
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/* Missing */
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GB_IO_WAV_START = 0x30, // Wave pattern start
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GB_IO_WAV_END = 0x3f, // Wave pattern end
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/* Graphics */
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GB_IO_LCDC = 0x40, // LCD Control (R/W)
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GB_IO_STAT = 0x41, // LCDC Status (R/W)
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GB_IO_SCY = 0x42, // Scroll Y (R/W)
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GB_IO_SCX = 0x43, // Scroll X (R/W)
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GB_IO_LY = 0x44, // LCDC Y-Coordinate (R)
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GB_IO_LYC = 0x45, // LY Compare (R/W)
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GB_IO_DMA = 0x46, // DMA Transfer and Start Address (W)
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GB_IO_BGP = 0x47, // BG Palette Data (R/W) - Non CGB Mode Only
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GB_IO_OBP0 = 0x48, // Object Palette 0 Data (R/W) - Non CGB Mode Only
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GB_IO_OBP1 = 0x49, // Object Palette 1 Data (R/W) - Non CGB Mode Only
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GB_IO_WY = 0x4a, // Window Y Position (R/W)
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GB_IO_WX = 0x4b, // Window X Position minus 7 (R/W)
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2016-04-05 20:21:51 +00:00
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// Has some undocumented compatibility flags written at boot.
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// Unfortunately it is not readable or writable after boot has finished, so research of this
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// register is quite limited. The value written to this register, however, can be controlled
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// in some cases.
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GB_IO_DMG_EMULATION = 0x4c,
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2016-03-30 20:07:55 +00:00
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/* General CGB features */
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GB_IO_KEY1 = 0x4d, // CGB Mode Only - Prepare Speed Switch
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/* Missing */
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GB_IO_VBK = 0x4f, // CGB Mode Only - VRAM Bank
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GB_IO_BIOS = 0x50, // Write to disable the BIOS mapping
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/* CGB DMA */
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GB_IO_HDMA1 = 0x51, // CGB Mode Only - New DMA Source, High
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GB_IO_HDMA2 = 0x52, // CGB Mode Only - New DMA Source, Low
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GB_IO_HDMA3 = 0x53, // CGB Mode Only - New DMA Destination, High
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GB_IO_HDMA4 = 0x54, // CGB Mode Only - New DMA Destination, Low
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GB_IO_HDMA5 = 0x55, // CGB Mode Only - New DMA Length/Mode/Start
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/* IR */
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GB_IO_RP = 0x56, // CGB Mode Only - Infrared Communications Port
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/* Missing */
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/* CGB Paletts */
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GB_IO_BGPI = 0x68, // CGB Mode Only - Background Palette Index
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GB_IO_BGPD = 0x69, // CGB Mode Only - Background Palette Data
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GB_IO_OBPI = 0x6a, // CGB Mode Only - Sprite Palette Index
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GB_IO_OBPD = 0x6b, // CGB Mode Only - Sprite Palette Data
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2016-04-05 20:21:51 +00:00
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// 1 is written for DMG ROMs on a CGB. Does not appear to have an effect.
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GB_IO_DMG_EMULATION_INDICATION = 0x6c, // (FEh) Bit 0 (Read/Write)
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2016-03-30 20:07:55 +00:00
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/* Missing */
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GB_IO_SVBK = 0x70, // CGB Mode Only - WRAM Bank
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GB_IO_UNKNOWN2 = 0x72, // (00h) - Bit 0-7 (Read/Write)
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GB_IO_UNKNOWN3 = 0x73, // (00h) - Bit 0-7 (Read/Write)
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GB_IO_UNKNOWN4 = 0x74, // (00h) - Bit 0-7 (Read/Write) - CGB Mode Only
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GB_IO_UNKNOWN5 = 0x75, // (8Fh) - Bit 4-6 (Read/Write)
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GB_IO_PCM_12 = 0x76, // Channels 1 and 2 amplitudes
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GB_IO_PCM_34 = 0x77, // Channels 3 and 4 amplitudes
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GB_IO_UNKNOWN8 = 0x7F, // Unknown, write only
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};
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typedef enum {
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GB_LOG_BOLD = 1,
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GB_LOG_DASHED_UNDERLINE = 2,
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GB_LOG_UNDERLINE = 4,
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GB_LOG_UNDERLINE_MASK = GB_LOG_DASHED_UNDERLINE | GB_LOG_UNDERLINE
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2016-06-18 17:29:11 +00:00
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} GB_log_attributes;
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2016-03-30 20:07:55 +00:00
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2017-04-17 17:16:17 +00:00
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#ifdef GB_INTERNAL
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#define LCDC_PERIOD 70224
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#define CPU_FREQUENCY 0x400000
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#define DIV_CYCLES (0x100)
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#define INTERNAL_DIV_CYCLES (0x40000)
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2017-10-12 14:22:22 +00:00
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#if !defined(MIN)
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#define MIN(A,B) ({ __typeof__(A) __a = (A); __typeof__(B) __b = (B); __a < __b ? __a : __b; })
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#endif
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#if !defined(MAX)
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#define MAX(A,B) ({ __typeof__(A) __a = (A); __typeof__(B) __b = (B); __a < __b ? __b : __a; })
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#endif
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2017-04-17 17:16:17 +00:00
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#endif
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2016-03-30 20:07:55 +00:00
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typedef void (*GB_vblank_callback_t)(GB_gameboy_t *gb);
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2016-06-18 17:29:11 +00:00
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typedef void (*GB_log_callback_t)(GB_gameboy_t *gb, const char *string, GB_log_attributes attributes);
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2016-03-30 20:07:55 +00:00
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typedef char *(*GB_input_callback_t)(GB_gameboy_t *gb);
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2016-06-18 17:29:11 +00:00
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typedef uint32_t (*GB_rgb_encode_callback_t)(GB_gameboy_t *gb, uint8_t r, uint8_t g, uint8_t b);
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2016-07-20 22:03:13 +00:00
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typedef void (*GB_infrared_callback_t)(GB_gameboy_t *gb, bool on, long cycles_since_last_update);
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2016-10-22 12:37:03 +00:00
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typedef void (*GB_rumble_callback_t)(GB_gameboy_t *gb, bool rumble_on);
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2016-11-11 23:58:53 +00:00
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typedef void (*GB_serial_transfer_start_callback_t)(GB_gameboy_t *gb, uint8_t byte_to_send);
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typedef uint8_t (*GB_serial_transfer_end_callback_t)(GB_gameboy_t *gb);
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2016-07-20 22:03:13 +00:00
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typedef struct {
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bool state;
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long delay;
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} GB_ir_queue_item_t;
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2016-07-06 21:29:25 +00:00
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struct GB_breakpoint_s;
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struct GB_watchpoint_s;
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2018-03-03 13:47:36 +00:00
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typedef struct {
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uint8_t pixel; // Color, 0-3
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uint8_t palette; // Palette, 0 - 7 (CGB); 0-1 in DMG (or just 0 for BG)
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uint8_t priority; // Sprite priority – 0 in DMG, OAM index in CGB
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bool bg_priority; // For sprite FIFO – the BG priority bit. For the BG FIFO – the CGB attributes priority bit
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} GB_fifo_item_t;
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2018-04-06 15:26:04 +00:00
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#define GB_FIFO_LENGTH 16
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2018-03-03 13:47:36 +00:00
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typedef struct {
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2018-04-06 15:26:04 +00:00
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GB_fifo_item_t fifo[GB_FIFO_LENGTH];
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2018-03-03 13:47:36 +00:00
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uint8_t read_end;
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uint8_t write_end;
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} GB_fifo_t;
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2016-06-11 11:52:09 +00:00
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/* When state saving, each section is dumped independently of other sections.
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This allows adding data to the end of the section without worrying about future compatibility.
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2016-06-18 17:29:11 +00:00
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Some other changes might be "safe" as well.
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This struct is not packed, but dumped sections exclusively use types that have the same alignment in both 32 and 64
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bit platforms. */
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/* We make sure bool is 1 for cross-platform save state compatibility. */
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/* Todo: We might want to typedef our own bool if this prevents SameBoy from working on specific platforms. */
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_Static_assert(sizeof(bool) == 1, "sizeof(bool) != 1");
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2016-06-11 11:52:09 +00:00
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2017-04-17 17:16:17 +00:00
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#ifdef GB_INTERNAL
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struct GB_gameboy_s {
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#else
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struct GB_gameboy_internal_s {
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#endif
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2016-06-11 11:52:09 +00:00
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GB_SECTION(header,
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2016-06-18 17:29:11 +00:00
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/* The magic makes sure a state file is:
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- Indeed a SameBoy state file.
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- Has the same endianess has the current platform. */
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2017-02-24 13:14:00 +00:00
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volatile uint32_t magic;
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2016-06-18 17:29:11 +00:00
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/* The version field makes sure we don't load save state files with a completely different structure.
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This happens when struct fields are removed/resized in an backward incompatible manner. */
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uint32_t version;
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2016-06-11 11:52:09 +00:00
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);
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GB_SECTION(core_state,
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/* Registers */
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2016-06-18 17:29:11 +00:00
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uint16_t pc;
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2016-10-21 21:49:32 +00:00
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union {
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uint16_t registers[GB_REGISTERS_16_BIT];
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struct {
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uint16_t af,
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bc,
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de,
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hl,
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sp;
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};
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struct {
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#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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uint8_t a, f,
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b, c,
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d, e,
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h, l;
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#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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uint8_t f, a,
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c, b,
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e, d,
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l, h;
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#else
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#error Unable to detect endianess
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#endif
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};
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};
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2016-08-05 13:36:38 +00:00
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uint8_t ime;
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2016-06-18 17:29:11 +00:00
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uint8_t interrupt_enable;
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uint8_t cgb_ram_bank;
|
2016-06-11 11:52:09 +00:00
|
|
|
|
|
|
|
|
|
/* CPU and General Hardware Flags*/
|
|
|
|
|
bool cgb_mode;
|
|
|
|
|
bool is_cgb;
|
|
|
|
|
bool cgb_double_speed;
|
|
|
|
|
bool halted;
|
|
|
|
|
bool stopped;
|
2016-06-18 17:29:11 +00:00
|
|
|
|
bool boot_rom_finished;
|
2018-02-25 20:32:41 +00:00
|
|
|
|
bool ime_toggle; /* ei has delayed a effect.*/
|
2016-09-21 22:51:09 +00:00
|
|
|
|
bool halt_bug;
|
2016-07-18 19:05:11 +00:00
|
|
|
|
|
2017-01-13 19:27:37 +00:00
|
|
|
|
/* Misc state */
|
2016-07-18 19:05:11 +00:00
|
|
|
|
bool infrared_input;
|
2017-01-13 19:27:37 +00:00
|
|
|
|
GB_printer_t printer;
|
2016-06-11 11:52:09 +00:00
|
|
|
|
);
|
2016-03-30 20:07:55 +00:00
|
|
|
|
|
2016-08-03 20:31:10 +00:00
|
|
|
|
/* DMA and HDMA */
|
|
|
|
|
GB_SECTION(dma,
|
2016-06-11 11:52:09 +00:00
|
|
|
|
bool hdma_on;
|
|
|
|
|
bool hdma_on_hblank;
|
2016-06-18 17:29:11 +00:00
|
|
|
|
uint8_t hdma_steps_left;
|
2018-04-13 11:41:39 +00:00
|
|
|
|
int16_t hdma_cycles; // in 8MHz units
|
2016-06-18 17:29:11 +00:00
|
|
|
|
uint16_t hdma_current_src, hdma_current_dest;
|
2016-08-03 20:31:10 +00:00
|
|
|
|
|
|
|
|
|
uint8_t dma_steps_left;
|
|
|
|
|
uint8_t dma_current_dest;
|
|
|
|
|
uint16_t dma_current_src;
|
2016-08-06 10:57:38 +00:00
|
|
|
|
int16_t dma_cycles;
|
2016-08-06 11:24:43 +00:00
|
|
|
|
bool is_dma_restarting;
|
2018-02-25 20:32:41 +00:00
|
|
|
|
uint8_t last_opcode_read; /* Required to emulte HDMA reads from Exxx */
|
2018-03-19 18:01:31 +00:00
|
|
|
|
bool hdma_starting;
|
2016-06-11 11:52:09 +00:00
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
/* MBC */
|
|
|
|
|
GB_SECTION(mbc,
|
2016-06-18 17:29:11 +00:00
|
|
|
|
uint16_t mbc_rom_bank;
|
|
|
|
|
uint8_t mbc_ram_bank;
|
|
|
|
|
uint32_t mbc_ram_size;
|
2016-06-11 11:52:09 +00:00
|
|
|
|
bool mbc_ram_enable;
|
2016-07-09 14:34:55 +00:00
|
|
|
|
union {
|
|
|
|
|
struct {
|
|
|
|
|
uint8_t bank_low:5;
|
2017-06-20 22:07:11 +00:00
|
|
|
|
uint8_t bank_high:2;
|
2016-07-09 14:34:55 +00:00
|
|
|
|
uint8_t mode:1;
|
|
|
|
|
} mbc1;
|
|
|
|
|
|
|
|
|
|
struct {
|
|
|
|
|
uint8_t rom_bank:4;
|
|
|
|
|
} mbc2;
|
|
|
|
|
|
|
|
|
|
struct {
|
|
|
|
|
uint8_t rom_bank:7;
|
|
|
|
|
uint8_t padding:1;
|
|
|
|
|
uint8_t ram_bank:4;
|
|
|
|
|
} mbc3;
|
|
|
|
|
|
|
|
|
|
struct {
|
|
|
|
|
uint8_t rom_bank_low;
|
|
|
|
|
uint8_t rom_bank_high:1;
|
|
|
|
|
uint8_t ram_bank:4;
|
|
|
|
|
} mbc5;
|
2017-02-16 19:07:35 +00:00
|
|
|
|
|
|
|
|
|
struct {
|
|
|
|
|
uint8_t bank_low:6;
|
|
|
|
|
uint8_t bank_high:3;
|
|
|
|
|
uint8_t mode:1;
|
|
|
|
|
} huc1;
|
2016-10-17 15:51:43 +00:00
|
|
|
|
|
|
|
|
|
struct {
|
|
|
|
|
uint8_t rom_bank;
|
|
|
|
|
uint8_t ram_bank;
|
|
|
|
|
} huc3;
|
2016-07-09 14:34:55 +00:00
|
|
|
|
};
|
|
|
|
|
uint16_t mbc_rom0_bank; /* For some MBC1 wirings. */
|
2016-10-02 00:40:11 +00:00
|
|
|
|
bool camera_registers_mapped;
|
2016-10-02 14:14:58 +00:00
|
|
|
|
uint8_t camera_registers[0x36];
|
2016-10-22 12:37:03 +00:00
|
|
|
|
bool rumble_state;
|
2016-06-11 11:52:09 +00:00
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* HRAM and HW Registers */
|
|
|
|
|
GB_SECTION(hram,
|
2016-06-18 17:29:11 +00:00
|
|
|
|
uint8_t hram[0xFFFF - 0xFF80];
|
|
|
|
|
uint8_t io_registers[0x80];
|
2016-06-11 11:52:09 +00:00
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
/* Timing */
|
|
|
|
|
GB_SECTION(timing,
|
2018-02-24 22:48:45 +00:00
|
|
|
|
GB_UNIT(display);
|
2018-02-23 11:16:05 +00:00
|
|
|
|
GB_UNIT(div);
|
|
|
|
|
uint32_t div_counter;
|
2016-08-06 10:56:29 +00:00
|
|
|
|
uint8_t tima_reload_state; /* After TIMA overflows, it becomes 0 for 4 cycles before actually reloading. */
|
2017-09-22 21:25:21 +00:00
|
|
|
|
uint16_t serial_cycles;
|
2017-06-23 14:58:04 +00:00
|
|
|
|
uint16_t serial_length;
|
2016-06-11 11:52:09 +00:00
|
|
|
|
);
|
2016-03-30 20:07:55 +00:00
|
|
|
|
|
2016-06-11 11:52:09 +00:00
|
|
|
|
/* APU */
|
|
|
|
|
GB_SECTION(apu,
|
|
|
|
|
GB_apu_t apu;
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
/* RTC */
|
|
|
|
|
GB_SECTION(rtc,
|
|
|
|
|
union {
|
|
|
|
|
struct {
|
2016-08-21 19:33:57 +00:00
|
|
|
|
uint8_t seconds;
|
|
|
|
|
uint8_t minutes;
|
|
|
|
|
uint8_t hours;
|
|
|
|
|
uint8_t days;
|
|
|
|
|
uint8_t high;
|
2016-06-11 11:52:09 +00:00
|
|
|
|
};
|
2016-08-21 19:33:57 +00:00
|
|
|
|
uint8_t data[5];
|
|
|
|
|
} rtc_real, rtc_latched;
|
2016-06-11 11:52:09 +00:00
|
|
|
|
time_t last_rtc_second;
|
2016-08-21 19:33:57 +00:00
|
|
|
|
bool rtc_latch;
|
2016-06-11 11:52:09 +00:00
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
/* Video Display */
|
|
|
|
|
GB_SECTION(video,
|
2016-06-18 17:29:11 +00:00
|
|
|
|
uint32_t vram_size; // Different between CGB and DMG
|
|
|
|
|
uint8_t cgb_vram_bank;
|
|
|
|
|
uint8_t oam[0xA0];
|
2017-04-19 20:26:39 +00:00
|
|
|
|
uint8_t background_palettes_data[0x40];
|
|
|
|
|
uint8_t sprite_palettes_data[0x40];
|
2018-02-24 22:48:45 +00:00
|
|
|
|
uint8_t position_in_line;
|
2016-06-11 11:52:09 +00:00
|
|
|
|
bool stat_interrupt_line;
|
2016-06-18 17:29:11 +00:00
|
|
|
|
uint8_t effective_scx;
|
2017-08-19 22:34:12 +00:00
|
|
|
|
uint8_t wy_diff;
|
2017-06-03 17:06:52 +00:00
|
|
|
|
/* The LCDC will skip the first frame it renders after turning it on.
|
|
|
|
|
On the CGB, a frame is not skipped if the previous frame was skipped as well.
|
2017-06-03 13:42:42 +00:00
|
|
|
|
See https://www.reddit.com/r/EmuDev/comments/6exyxu/ */
|
|
|
|
|
enum {
|
2017-06-03 17:06:52 +00:00
|
|
|
|
GB_FRAMESKIP_LCD_TURNED_ON, // On a DMG, the LCD renders a blank screen during this state,
|
|
|
|
|
// on a CGB, the previous frame is repeated (which might be
|
|
|
|
|
// blank if the LCD was off for more than a few cycles)
|
|
|
|
|
GB_FRAMESKIP_FIRST_FRAME_SKIPPED, // This state is 'skipped' when emulating a DMG
|
2017-06-03 13:42:42 +00:00
|
|
|
|
GB_FRAMESKIP_SECOND_FRAME_RENDERED,
|
|
|
|
|
} frame_skip_state;
|
2017-06-18 18:27:07 +00:00
|
|
|
|
bool oam_read_blocked;
|
|
|
|
|
bool vram_read_blocked;
|
|
|
|
|
bool oam_write_blocked;
|
|
|
|
|
bool vram_write_blocked;
|
2017-08-19 22:34:12 +00:00
|
|
|
|
bool window_disabled_while_active;
|
2018-02-24 22:48:45 +00:00
|
|
|
|
uint8_t current_line;
|
|
|
|
|
uint16_t ly_for_comparison;
|
2018-03-03 13:47:36 +00:00
|
|
|
|
GB_fifo_t bg_fifo, oam_fifo;
|
|
|
|
|
uint8_t fetcher_x;
|
2018-03-03 18:51:38 +00:00
|
|
|
|
uint8_t fetcher_y;
|
2018-03-03 13:47:36 +00:00
|
|
|
|
uint16_t cycles_for_line;
|
|
|
|
|
uint8_t current_tile;
|
2018-03-09 16:52:36 +00:00
|
|
|
|
uint8_t current_tile_attributes;
|
2018-03-03 13:47:36 +00:00
|
|
|
|
uint8_t current_tile_data[2];
|
2018-04-06 16:29:49 +00:00
|
|
|
|
uint8_t fetcher_state;
|
2018-03-09 15:10:19 +00:00
|
|
|
|
bool bg_fifo_paused;
|
|
|
|
|
bool oam_fifo_paused;
|
2018-03-03 17:36:21 +00:00
|
|
|
|
bool in_window;
|
2018-03-04 20:21:56 +00:00
|
|
|
|
uint8_t visible_objs[10];
|
2018-03-27 19:13:08 +00:00
|
|
|
|
uint8_t obj_comperators[10];
|
2018-03-04 20:21:56 +00:00
|
|
|
|
uint8_t n_visible_objs;
|
2018-03-23 16:07:14 +00:00
|
|
|
|
uint8_t oam_search_index;
|
2018-03-27 12:46:00 +00:00
|
|
|
|
uint8_t accessed_oam_row;
|
2018-03-30 14:06:27 +00:00
|
|
|
|
uint8_t extra_penalty_for_sprite_at_0;
|
2018-03-31 10:18:02 +00:00
|
|
|
|
bool is_first_line_mode2;
|
2018-04-01 18:45:56 +00:00
|
|
|
|
bool oam_interrupt_line;
|
2016-06-11 11:52:09 +00:00
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
/* Unsaved data. This includes all pointers, as well as everything that shouldn't be on a save state */
|
2017-04-17 17:16:17 +00:00
|
|
|
|
/* This data is reserved on reset and must come last in the struct */
|
|
|
|
|
GB_SECTION(unsaved,
|
|
|
|
|
/* ROM */
|
|
|
|
|
uint8_t *rom;
|
|
|
|
|
uint32_t rom_size;
|
|
|
|
|
const GB_cartridge_t *cartridge_type;
|
|
|
|
|
enum {
|
|
|
|
|
GB_STANDARD_MBC1_WIRING,
|
|
|
|
|
GB_MBC1M_WIRING,
|
|
|
|
|
} mbc1_wiring;
|
|
|
|
|
|
2018-04-14 10:23:33 +00:00
|
|
|
|
unsigned pending_cycles;
|
|
|
|
|
|
2017-04-17 17:16:17 +00:00
|
|
|
|
/* Various RAMs */
|
|
|
|
|
uint8_t *ram;
|
|
|
|
|
uint8_t *vram;
|
|
|
|
|
uint8_t *mbc_ram;
|
|
|
|
|
|
|
|
|
|
/* I/O */
|
|
|
|
|
uint32_t *screen;
|
2017-10-12 14:22:22 +00:00
|
|
|
|
uint32_t background_palettes_rgb[0x20];
|
|
|
|
|
uint32_t sprite_palettes_rgb[0x20];
|
|
|
|
|
GB_color_correction_mode_t color_correction_mode;
|
2017-04-17 17:16:17 +00:00
|
|
|
|
bool keys[GB_KEY_MAX];
|
2017-04-21 13:00:53 +00:00
|
|
|
|
|
|
|
|
|
/* Timing */
|
|
|
|
|
uint64_t last_sync;
|
2018-02-20 19:17:12 +00:00
|
|
|
|
uint64_t cycles_since_last_sync; // In 8MHz units
|
2017-04-17 17:16:17 +00:00
|
|
|
|
|
2017-04-21 13:00:53 +00:00
|
|
|
|
/* Audio */
|
2017-07-21 20:06:02 +00:00
|
|
|
|
GB_apu_output_t apu_output;
|
2017-04-17 17:16:17 +00:00
|
|
|
|
|
|
|
|
|
/* Callbacks */
|
|
|
|
|
void *user_data;
|
|
|
|
|
GB_log_callback_t log_callback;
|
|
|
|
|
GB_input_callback_t input_callback;
|
|
|
|
|
GB_input_callback_t async_input_callback;
|
|
|
|
|
GB_rgb_encode_callback_t rgb_encode_callback;
|
|
|
|
|
GB_vblank_callback_t vblank_callback;
|
|
|
|
|
GB_infrared_callback_t infrared_callback;
|
|
|
|
|
GB_camera_get_pixel_callback_t camera_get_pixel_callback;
|
|
|
|
|
GB_camera_update_request_callback_t camera_update_request_callback;
|
|
|
|
|
GB_rumble_callback_t rumble_callback;
|
|
|
|
|
GB_serial_transfer_start_callback_t serial_transfer_start_callback;
|
|
|
|
|
GB_serial_transfer_end_callback_t serial_transfer_end_callback;
|
2017-04-21 13:00:53 +00:00
|
|
|
|
|
2017-04-17 17:16:17 +00:00
|
|
|
|
/* IR */
|
2018-02-20 19:17:12 +00:00
|
|
|
|
long cycles_since_ir_change; // In 8MHz units
|
|
|
|
|
long cycles_since_input_ir_change; // In 8MHz units
|
2017-04-17 17:16:17 +00:00
|
|
|
|
GB_ir_queue_item_t ir_queue[GB_MAX_IR_QUEUE];
|
|
|
|
|
size_t ir_queue_length;
|
|
|
|
|
|
|
|
|
|
/*** Debugger ***/
|
|
|
|
|
volatile bool debug_stopped, debug_disable;
|
|
|
|
|
bool debug_fin_command, debug_next_command;
|
|
|
|
|
|
|
|
|
|
/* Breakpoints */
|
|
|
|
|
uint16_t n_breakpoints;
|
|
|
|
|
struct GB_breakpoint_s *breakpoints;
|
|
|
|
|
|
|
|
|
|
/* SLD (Todo: merge with backtrace) */
|
|
|
|
|
bool stack_leak_detection;
|
|
|
|
|
int debug_call_depth;
|
|
|
|
|
uint16_t sp_for_call_depth[0x200]; /* Should be much more than enough */
|
|
|
|
|
uint16_t addr_for_call_depth[0x200];
|
|
|
|
|
|
|
|
|
|
/* Backtrace */
|
|
|
|
|
unsigned int backtrace_size;
|
|
|
|
|
uint16_t backtrace_sps[0x200];
|
|
|
|
|
struct {
|
|
|
|
|
uint16_t bank;
|
|
|
|
|
uint16_t addr;
|
|
|
|
|
} backtrace_returns[0x200];
|
|
|
|
|
|
|
|
|
|
/* Watchpoints */
|
|
|
|
|
uint16_t n_watchpoints;
|
|
|
|
|
struct GB_watchpoint_s *watchpoints;
|
|
|
|
|
|
|
|
|
|
/* Symbol tables */
|
|
|
|
|
GB_symbol_map_t *bank_symbols[0x200];
|
|
|
|
|
GB_reversed_symbol_map_t reversed_symbol_map;
|
|
|
|
|
|
|
|
|
|
/* Ticks command */
|
|
|
|
|
unsigned long debugger_ticks;
|
2018-02-10 12:42:14 +00:00
|
|
|
|
|
|
|
|
|
/* Rewind */
|
|
|
|
|
#define GB_REWIND_FRAMES_PER_KEY 255
|
|
|
|
|
size_t rewind_buffer_length;
|
|
|
|
|
struct {
|
|
|
|
|
uint8_t *key_state;
|
|
|
|
|
uint8_t *compressed_states[GB_REWIND_FRAMES_PER_KEY];
|
|
|
|
|
unsigned pos;
|
|
|
|
|
} *rewind_sequences; // lasts about 4 seconds
|
|
|
|
|
size_t rewind_pos;
|
2017-04-17 17:16:17 +00:00
|
|
|
|
|
|
|
|
|
/* Misc */
|
|
|
|
|
bool turbo;
|
|
|
|
|
bool turbo_dont_skip;
|
|
|
|
|
bool disable_rendering;
|
|
|
|
|
uint32_t ram_size; // Different between CGB and DMG
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uint8_t boot_rom[0x900];
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bool vblank_just_occured; // For slow operations involving syscalls; these should only run once per vblank
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2018-02-20 19:17:12 +00:00
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uint8_t cycles_since_run; // How many cycles have passed since the last call to GB_run(), in 8MHz units
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2018-02-10 21:30:30 +00:00
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double clock_multiplier;
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2017-04-17 17:16:17 +00:00
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);
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};
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#ifndef GB_INTERNAL
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struct GB_gameboy_s {
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char __internal[sizeof(struct GB_gameboy_internal_s)];
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};
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#endif
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2016-06-11 11:52:09 +00:00
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2016-03-30 20:07:55 +00:00
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#ifndef __printflike
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/* Missing from Linux headers. */
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#define __printflike(fmtarg, firstvararg) \
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__attribute__((__format__ (__printf__, fmtarg, firstvararg)))
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#endif
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2016-06-18 17:29:11 +00:00
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void GB_init(GB_gameboy_t *gb);
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void GB_init_cgb(GB_gameboy_t *gb);
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2017-04-19 18:55:58 +00:00
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bool GB_is_inited(GB_gameboy_t *gb);
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2017-04-19 20:26:39 +00:00
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bool GB_is_cgb(GB_gameboy_t *gb);
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2016-06-18 17:29:11 +00:00
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void GB_free(GB_gameboy_t *gb);
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2017-04-17 17:16:17 +00:00
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void GB_reset(GB_gameboy_t *gb);
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void GB_switch_model_and_reset(GB_gameboy_t *gb, bool is_cgb);
|
2018-01-31 13:18:04 +00:00
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/* Returns the time passed, in 4MHz ticks. */
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uint8_t GB_run(GB_gameboy_t *gb);
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2017-04-24 21:19:10 +00:00
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/* Returns the time passed since the last frame, in nanoseconds */
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uint64_t GB_run_frame(GB_gameboy_t *gb);
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2017-04-19 18:55:58 +00:00
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2017-04-19 20:26:39 +00:00
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typedef enum {
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GB_DIRECT_ACCESS_ROM,
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GB_DIRECT_ACCESS_RAM,
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GB_DIRECT_ACCESS_CART_RAM,
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GB_DIRECT_ACCESS_VRAM,
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GB_DIRECT_ACCESS_HRAM,
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GB_DIRECT_ACCESS_IO, /* Warning: Some registers can only be read/written correctly via GB_memory_read/write. */
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GB_DIRECT_ACCESS_BOOTROM,
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GB_DIRECT_ACCESS_OAM,
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GB_DIRECT_ACCESS_BGP,
|
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GB_DIRECT_ACCESS_OBP,
|
2017-10-12 19:49:39 +00:00
|
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|
GB_DIRECT_ACCESS_IE,
|
2017-04-19 20:26:39 +00:00
|
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|
|
} GB_direct_access_t;
|
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|
/* Returns a mutable pointer to various hardware memories. If that memory is banked, the current bank
|
|
|
|
|
is returned at *bank, even if only a portion of the memory is banked. */
|
|
|
|
|
void *GB_get_direct_access(GB_gameboy_t *gb, GB_direct_access_t access, size_t *size, uint16_t *bank);
|
|
|
|
|
|
2017-04-19 18:55:58 +00:00
|
|
|
|
void *GB_get_user_data(GB_gameboy_t *gb);
|
|
|
|
|
void GB_set_user_data(GB_gameboy_t *gb, void *data);
|
|
|
|
|
|
2017-10-12 19:06:01 +00:00
|
|
|
|
|
2017-04-23 08:50:07 +00:00
|
|
|
|
|
2016-06-18 17:29:11 +00:00
|
|
|
|
int GB_load_boot_rom(GB_gameboy_t *gb, const char *path);
|
2017-10-12 19:06:01 +00:00
|
|
|
|
void GB_load_boot_rom_from_buffer(GB_gameboy_t *gb, const unsigned char *buffer, size_t size);
|
2016-06-18 17:29:11 +00:00
|
|
|
|
int GB_load_rom(GB_gameboy_t *gb, const char *path);
|
2017-04-19 18:55:58 +00:00
|
|
|
|
|
2016-06-18 17:29:11 +00:00
|
|
|
|
int GB_save_battery(GB_gameboy_t *gb, const char *path);
|
|
|
|
|
void GB_load_battery(GB_gameboy_t *gb, const char *path);
|
2017-04-19 18:55:58 +00:00
|
|
|
|
|
|
|
|
|
void GB_set_turbo_mode(GB_gameboy_t *gb, bool on, bool no_frame_skip);
|
|
|
|
|
void GB_set_rendering_disabled(GB_gameboy_t *gb, bool disabled);
|
|
|
|
|
|
|
|
|
|
void GB_log(GB_gameboy_t *gb, const char *fmt, ...) __printflike(2, 3);
|
|
|
|
|
void GB_attributed_log(GB_gameboy_t *gb, GB_log_attributes attributes, const char *fmt, ...) __printflike(3, 4);
|
|
|
|
|
|
2016-06-18 17:29:11 +00:00
|
|
|
|
void GB_set_pixels_output(GB_gameboy_t *gb, uint32_t *output);
|
2017-04-19 18:55:58 +00:00
|
|
|
|
|
|
|
|
|
void GB_set_infrared_input(GB_gameboy_t *gb, bool state);
|
2018-02-20 19:17:12 +00:00
|
|
|
|
void GB_queue_infrared_input(GB_gameboy_t *gb, bool state, long cycles_after_previous_change); /* In 8MHz units*/
|
2017-04-19 18:55:58 +00:00
|
|
|
|
|
2016-06-18 17:29:11 +00:00
|
|
|
|
void GB_set_vblank_callback(GB_gameboy_t *gb, GB_vblank_callback_t callback);
|
|
|
|
|
void GB_set_log_callback(GB_gameboy_t *gb, GB_log_callback_t callback);
|
|
|
|
|
void GB_set_input_callback(GB_gameboy_t *gb, GB_input_callback_t callback);
|
2016-07-17 21:39:43 +00:00
|
|
|
|
void GB_set_async_input_callback(GB_gameboy_t *gb, GB_input_callback_t callback);
|
2016-06-18 17:29:11 +00:00
|
|
|
|
void GB_set_rgb_encode_callback(GB_gameboy_t *gb, GB_rgb_encode_callback_t callback);
|
2016-07-18 19:05:11 +00:00
|
|
|
|
void GB_set_infrared_callback(GB_gameboy_t *gb, GB_infrared_callback_t callback);
|
2016-10-22 12:37:03 +00:00
|
|
|
|
void GB_set_rumble_callback(GB_gameboy_t *gb, GB_rumble_callback_t callback);
|
2016-11-11 23:58:53 +00:00
|
|
|
|
|
|
|
|
|
/* These APIs are used when using internal clock */
|
|
|
|
|
void GB_set_serial_transfer_start_callback(GB_gameboy_t *gb, GB_serial_transfer_start_callback_t callback);
|
|
|
|
|
void GB_set_serial_transfer_end_callback(GB_gameboy_t *gb, GB_serial_transfer_end_callback_t callback);
|
|
|
|
|
|
|
|
|
|
/* These APIs are used when using external clock */
|
|
|
|
|
uint8_t GB_serial_get_data(GB_gameboy_t *gb);
|
|
|
|
|
void GB_serial_set_data(GB_gameboy_t *gb, uint8_t data);
|
2017-04-19 18:55:58 +00:00
|
|
|
|
|
2017-01-13 19:27:37 +00:00
|
|
|
|
void GB_disconnect_serial(GB_gameboy_t *gb);
|
2017-02-24 13:14:00 +00:00
|
|
|
|
|
2018-02-10 21:30:30 +00:00
|
|
|
|
#ifdef GB_INTERNAL
|
|
|
|
|
uint32_t GB_get_clock_rate(GB_gameboy_t *gb);
|
|
|
|
|
#endif
|
|
|
|
|
void GB_set_clock_multiplier(GB_gameboy_t *gb, double multiplier);
|
|
|
|
|
|
2016-06-18 17:29:11 +00:00
|
|
|
|
#endif /* GB_h */
|