Commit Graph

84 Commits

Author SHA1 Message Date
Lior Halphon
713dc02e46 A bit tacky, but T-cycle accurate emulation of LYC write conflicts on the CGB. Only single speed mode verified. Closes #54 2018-05-11 12:38:55 +03:00
Lior Halphon
f1ec42d4ba H/GDMA was 4 times faster than it should have been. Made it also more accurate. Fixes #56 2018-04-13 14:41:39 +03:00
Lior Halphon
0c86ff1ee4 More CGB revision quirks 2018-04-06 04:00:37 +03:00
Lior Halphon
e163026ca9 The STAT bug does not occur during the glitched mode 0 2018-04-02 01:05:32 +03:00
Lior Halphon
7671648fca Simplified a function 2018-03-27 19:06:36 +03:00
Lior Halphon
4cbade9a88 Function name change 2018-03-27 15:55:12 +03:00
Lior Halphon
4986930511 Mostly complete emulation of the OAM bug. Passes oam_bug-2. 2018-03-27 15:46:00 +03:00
Lior Halphon
18e32d1755 Merge branch 'master' into timing
# Conflicts:
#	Core/gb.c
2018-03-22 22:37:35 +02:00
Lior Halphon
577e23925b Fixed sources-dmgABCXmgbS 2018-03-22 20:09:01 +02:00
Lior Halphon
b702d56547 Merge branch 'master' into timing
# Conflicts:
#	Core/display.c
#	Core/z80_cpu.c
2018-03-01 21:22:33 +02:00
Lior Halphon
b02e40d5a2 Refinement to that last fix 2018-02-25 23:23:55 +02:00
Lior Halphon
90a943d05a Emulate an HDMA quirk required to properly emulate Aevilia 2018-02-25 22:32:41 +02:00
Lior Halphon
ef670986c6 Rewrote PPU (currently only emulates DMG correctly) to use the new timing mechanism. Removed “future interrupts” (No longer required because SameBoy is now T-cycle based) 2018-02-25 00:48:45 +02:00
Lior Halphon
42ab746a66 Starting to remove the delayed interrupts hack – done for timer interrupt, broken for display interrupts 2018-02-23 15:33:44 +02:00
Lior Halphon
c48097a484 Convert div counter to the SM mechanism 2018-02-23 13:16:05 +02:00
Lior Halphon
9802ca41dd Components not affected by CGB’s double speed mode now operate in 8MHz mode to theoretically make advance_cycles(gb, 1) safe. 2018-02-20 21:17:12 +02:00
Lior Halphon
f79af39ea2 More accurate emulation of the APU’s analog characteristics 2018-02-16 18:01:50 +02:00
Lior Halphon
441781cbe9 Libretro .o files are now in the build/obj folder and are suffixed with _libretro (since they have different compilation flags). This also lets us rename gbmemory.c/h back to its original name. 2017-10-12 19:42:30 +03:00
twinaphex
a7db98c22e Memory needs to be uniquely named for Android 2017-10-09 11:36:55 -05:00
twinaphex
09f4edda57 Comment out debugger code - add HAVE_DEBUGGER ifdef 2017-10-09 11:36:53 -05:00
Lior Halphon
b9bdd6c49c Merge branch 'master' into new_apu 2017-09-10 02:33:40 +03:00
Lior Halphon
1e90400916 Reimplemented delayed/future interrupts, currently correct only for CGB. 2017-09-09 13:32:12 +03:00
Lior Halphon
ba0e66a5b7 Merge branch 'master' into new_apu 2017-09-04 18:41:13 +03:00
Lior Halphon
9b490396bb Fixed timing when turning the LCD display on during double speed mode 2017-09-02 23:26:45 +03:00
Lior Halphon
e7d5cdbb42 Merge branch 'master' into new_apu 2017-08-20 01:37:33 +03:00
Lior Halphon
cbbaf2ee84 Refined Window behavior once more, Fixes #12 (While not breaking Donkey Kong or 007) 2017-08-20 01:34:12 +03:00
Lior Halphon
d43daed6a6 Merge branch 'master' into new_apu 2017-08-12 21:43:09 +03:00
Lior Halphon
7df4e56454 KEY1 is only writable in CGB mode; screen should be black is LCD is on while in stop mode. 2017-08-12 21:42:47 +03:00
Lior Halphon
baccf336d7 Complete rewrite of the APU. Channel 3 is complete and passes all the relevant tests from blargg’s suite, as well as PCM34-based tests. Actual sound output is basic and limited, though. 2017-07-21 19:06:55 +03:00
Lior Halphon
c4ccbd5cce Improved serial interrupt timing, fixes boot_sclk_align. 2017-06-23 17:58:04 +03:00
Lior Halphon
c59272d46d Misc minor fixes, fixes several Mooneye-GB tests 2017-06-21 20:39:23 +03:00
Lior Halphon
abf7efcc5a Fixed lcdon_write_timing. 2017-06-18 21:27:07 +03:00
Lior Halphon
86c9f9d89d Updated SameBoy to pass Mooneye-GB’s lcdon_timing test (on a DMG), as well as refined related CBG behaviors. 2017-06-17 22:17:58 +03:00
Lior Halphon
d72807dd67 Implemented LCD first-frame-skip behavior, fixes a visual glitch in Pokémon Pinball 2017-06-03 16:42:42 +03:00
Lior Halphon
c766704267 More accurate FPS capping that tracks time correctly even when the screen is off. Should also support restarting the LCD during blank to increase FPS to 63. 2017-04-21 16:00:53 +03:00
Lior Halphon
fb55c35f87 New APIs, Document.m no longer requires GB_INTERNAL, fixed a bug where the sprite viewer showed incorrect sprites for some CGB exclusive games. 2017-04-19 23:26:39 +03:00
Lior Halphon
a925ef130d Stabilizing API: New joypad, debugger and reset APIs; internal APIs and direct struct access are no longer available without defining GB_INTERNAL. The SDL port uses the new “public” APIs, as well as most of the non-debug Cocoa code. 2017-04-17 20:16:17 +03:00
Lior Halphon
55e54d9499 Refinements to DMG STAT write interrupt bug. Fixes stat_irq_blocking on DMG. 2017-02-25 21:56:46 +02:00
Lior Halphon
dbd04f09e8 HBlank HDMA should start instantly when starting during HBlank. Fixes 3-D Ultra Pinball. 2017-02-25 15:42:59 +02:00
Lior Halphon
a420cfd798 HUC1’s RAM Enable only controls writing 2017-02-23 00:27:08 +02:00
Lior Halphon
91513ced22 Minor adjustment to LCD timing after enabling it. 2017-02-20 14:20:45 +02:00
Lior Halphon
421d3b27f5 Correct emulation of HUC1 banks higher than 0x1F 2017-02-16 21:07:35 +02:00
Lior Halphon
4b6fda0cb6 Simplified HDMA and fixed the reading of the HDMA5 register 2017-02-08 21:58:15 +02:00
Lior Halphon
d5c9a52337 Fixed: HDMA registers were not being updated during transfer 2017-02-07 00:24:26 +02:00
Lior Halphon
22c34e1095 Serial API 2016-11-12 01:58:53 +02:00
Lior Halphon
47aaf44017 Rumble API 2016-10-22 15:37:03 +03:00
Lior Halphon
2d51d13479 Various optimizations 2016-10-22 02:18:29 +03:00
Lior Halphon
11f8c41305 Basic HUC3 support 2016-10-17 18:51:43 +03:00
Lior Halphon
fa35869bc4 Implemented DMG STAT-write interrupt bug, fixed Road Rash and Zero no Densetsu (These game do not work on CGBs) 2016-10-11 13:37:43 +03:00
Lior Halphon
ab5f66795a Gameboy Camera API 2016-10-02 17:14:58 +03:00