Lior Halphon
c342663200
Emulate serial bit shifting, update the serial API to use bits instead of bytes, update printer emulation and libretro to use the new API
2019-03-15 14:36:10 +02:00
Lior Halphon
ba5c07bed9
Correctly emulate speed switch timing
2019-01-13 01:09:41 +02:00
Lior Halphon
af0430dbc5
Unroll some loops in PPU code, more efficient timer handling
2018-12-31 22:06:20 +02:00
Lior Halphon
dbc338a887
Compensate for prefetch in DIV’s initial value
2018-09-15 00:47:26 +03:00
Lior Halphon
f64da1864f
APU glitch: When turning the APU on while DIV's bit 4 (or 5 in double speed mode), the first DIV/APU event is skipped.
2018-06-09 15:11:20 +03:00
Lior Halphon
be9df4d658
Added mechanism to handle MMIO read/write conflicts. Fixes #65
2018-04-14 17:57:00 +03:00
Lior Halphon
0d0d9ccdae
Fixed a timer regression, fixes timer_if in DMG mode. Relates to #54
2018-03-31 15:52:31 +03:00
Lior Halphon
c7ca786e77
Attempt to fix building using MINGW. Affects #55
2018-03-29 21:27:19 +03:00
Lior Halphon
4cf78139a8
Fixed a bug where SameBoy freezes for a while after leaving turbo mode
2018-03-27 23:33:31 +03:00
Lior Halphon
c11af7ea26
Fix CGB timings
2018-03-23 12:58:51 +03:00
Lior Halphon
544ca2be4c
Changing the timings of memory writes so they’re not effectively one T-cycle late. This screws up APU’s cycle accuracy for now.
2018-03-05 21:17:37 +02:00
Lior Halphon
ef670986c6
Rewrote PPU (currently only emulates DMG correctly) to use the new timing mechanism. Removed “future interrupts” (No longer required because SameBoy is now T-cycle based)
2018-02-25 00:48:45 +02:00
Lior Halphon
42ab746a66
Starting to remove the delayed interrupts hack – done for timer interrupt, broken for display interrupts
2018-02-23 15:33:44 +02:00
Lior Halphon
c48097a484
Convert div counter to the SM mechanism
2018-02-23 13:16:05 +02:00
Lior Halphon
9802ca41dd
Components not affected by CGB’s double speed mode now operate in 8MHz mode to theoretically make advance_cycles(gb, 1) safe.
2018-02-20 21:17:12 +02:00
Lior Halphon
afcc66fb3c
Added CPU under/over-clocking support in Core, add under-clocking hotkey in the Cocoa port, allow modifier keys to be configured as input keys in Cocoa.
2018-02-10 23:30:30 +02:00
Lior Halphon
95234036bb
Added return value to GB_run API.
2018-01-31 15:18:04 +02:00
Lior Halphon
6c97bb9052
Accidentally reversed ifdef condition
2017-10-13 17:28:32 +03:00
Lior Halphon
7c0ad24175
Added compilation flag to disable timekeeping for frontends that handle fps keeping on their own
2017-10-12 19:24:12 +03:00
twinaphex
aeea20ae9d
Comment out nsleep
2017-10-09 11:36:53 -05:00
radius
765a072c73
this fixes fast forwarding but probably has to change to a proper fix
2017-10-09 11:36:24 -05:00
Lior Halphon
b9bdd6c49c
Merge branch 'master' into new_apu
2017-09-10 02:33:40 +03:00
Lior Halphon
1e90400916
Reimplemented delayed/future interrupts, currently correct only for CGB.
2017-09-09 13:32:12 +03:00
Lior Halphon
0f643e01b7
Removing the delayed interrupt mechanism, research is not complete enough for implementation
2017-09-08 12:58:35 +03:00
Lior Halphon
ba0e66a5b7
Merge branch 'master' into new_apu
2017-09-04 18:41:13 +03:00
Lior Halphon
72d26c7046
Fixed obscure timer behavior, fixed regression in rapid_toggle.gb.
2017-09-04 18:40:43 +03:00
Lior Halphon
54eb51d8db
Refined timer interrupt timing
2017-09-02 22:08:20 +03:00
Lior Halphon
d65c2247e5
Added channel 1 and 2, fixed accuracy issues with channel 3
2017-07-27 23:11:33 +03:00
Lior Halphon
a19ee1e5e0
2MHz audio downscaling support. Implemented NR50 and NR51.
2017-07-21 23:17:48 +03:00
Lior Halphon
baccf336d7
Complete rewrite of the APU. Channel 3 is complete and passes all the relevant tests from blargg’s suite, as well as PCM34-based tests. Actual sound output is basic and limited, though.
2017-07-21 19:06:55 +03:00
Lior Halphon
c4ccbd5cce
Improved serial interrupt timing, fixes boot_sclk_align.
2017-06-23 17:58:04 +03:00
Lior Halphon
65b0dcb2c5
Fixed a bug where SameBoy freeze for a moment after leaving turbo mode
2017-06-03 17:02:12 +03:00
Lior Halphon
00623d4eea
- Added audio supersampling support to greatly improve audio quality.
...
- Fixed a bug where low sampling rate or disabled sound resulted in wrong APU behavior.
- Added API to get the current number of pending samples.
- This change broke save state compatibility with v0.8 and older
Closes #8 .
2017-05-12 17:11:55 +03:00
Lior Halphon
c766704267
More accurate FPS capping that tracks time correctly even when the screen is off. Should also support restarting the LCD during blank to increase FPS to 63.
2017-04-21 16:00:53 +03:00
Lior Halphon
a925ef130d
Stabilizing API: New joypad, debugger and reset APIs; internal APIs and direct struct access are no longer available without defining GB_INTERNAL. The SDL port uses the new “public” APIs, as well as most of the non-debug Cocoa code.
2017-04-17 20:16:17 +03:00
Lior Halphon
399e88d5fe
STAT timing and LCD interrupts rewritten, should be more accurate.
2017-02-19 02:22:50 +02:00
Lior Halphon
22c34e1095
Serial API
2016-11-12 01:58:53 +02:00
Lior Halphon
2d51d13479
Various optimizations
2016-10-22 02:18:29 +03:00
Lior Halphon
f88c9d299b
Merge branch 'master' into rateless_apu
2016-09-20 20:05:03 +03:00
Lior Halphon
71d4ba21f2
Added a tick-counting debugger command
2016-09-16 11:58:31 +03:00
Lior Halphon
b95860c034
Making the APU independent of sample rate
2016-09-13 16:55:26 +03:00
Lior Halphon
603b8969ab
Correct (disconnected) serial emulation.
2016-09-06 13:13:14 +03:00
Lior Halphon
ee4907949b
Support for RTC latching. Fixes #4 .
2016-08-21 22:33:57 +03:00
Lior Halphon
0f98ac5ff9
Emulate TIMA reloading
2016-08-06 13:56:29 +03:00
Lior Halphon
55cbe5d4d0
Accuracy improvements to timers
2016-08-06 00:24:12 +03:00
Lior Halphon
47e3300b66
Improved DMA accuracy, mooneyegb test ROMs no longer crash miserably. (but still fail)
2016-08-03 23:31:10 +03:00
Lior Halphon
185e71fe12
Improvements to IR API, since timing is VERY important
2016-07-21 01:03:13 +03:00
Lior Halphon
aa6438fa06
Async debugger commands
2016-07-18 00:46:45 +03:00
Lior Halphon
70bd90740a
Mass name and type changes. Save states are now compatible between 32- and 64-bit systems. Maybe.
2016-06-18 20:29:11 +03:00
Lior Halphon
0a09fba091
Correcting DIV and TIMA speed in CGB's double speed mode
2016-04-09 16:48:37 +03:00
