Lior Halphon
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9693b2de6a
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Refined the STAT bug behavior. Still not perfect.
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2018-05-26 17:06:49 +03:00 |
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Lior Halphon
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855ffb490a
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A HBlank interrupt cannot occur in the last M-cycle of HBlank. Correct emulation of STAT access conflicts on the CGB (Test: CPU-E, single speed only). Fixes a minor graphical glitch in Pokémon Puzzle Challenge.
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2018-05-25 23:42:36 +03:00 |
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Lior Halphon
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713dc02e46
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A bit tacky, but T-cycle accurate emulation of LYC write conflicts on the CGB. Only single speed mode verified. Closes #54
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2018-05-11 12:38:55 +03:00 |
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Lior Halphon
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af3554c1d1
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More accurate emulation of the LYC register and interrupt. (Still not perfect on a CGB)
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2018-04-27 13:40:39 +03:00 |
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Lior Halphon
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0f8385a798
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Refined line 153 behavior on a CGB. Verified on CGB-E.
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2018-04-25 00:08:06 +03:00 |
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Lior Halphon
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5be2b3db29
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It appears that OAM DMA blocks PPU access to OAM
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2018-04-07 13:59:36 +03:00 |
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Lior Halphon
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0725b008be
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Further simplifications
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2018-04-07 13:02:53 +03:00 |
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Lior Halphon
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097b768127
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Update comments
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2018-04-07 03:36:47 +03:00 |
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Lior Halphon
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9ce028056a
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Cleanup
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2018-04-07 03:26:10 +03:00 |
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Lior Halphon
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fed2556fc3
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More reasonable implementation of sprite timings
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2018-04-07 03:00:26 +03:00 |
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Lior Halphon
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0751eae90b
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Moved the fetcher state machine to another function
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2018-04-06 19:29:49 +03:00 |
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Lior Halphon
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0461fb5b2a
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Simplified FIFO logic
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2018-04-06 19:11:48 +03:00 |
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Lior Halphon
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cb01259073
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Fixed #61
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2018-04-06 11:37:49 +03:00 |
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Lior Halphon
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a6ed2029b7
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New information about PPU changes between CGB-B and CGB-E
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2018-04-06 03:19:47 +03:00 |
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Lior Halphon
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cc95c89d3c
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Surprise! The CGB has a 16-bit VRAM data bus
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2018-04-05 16:15:51 +03:00 |
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Lior Halphon
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9aadc80f75
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Implemented some obscure PPU rendering quirks, verified some timings
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2018-04-05 15:33:21 +03:00 |
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Lior Halphon
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d785e45308
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More accurate emulation of LCDC.0
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2018-04-05 12:27:01 +03:00 |
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Lior Halphon
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d8e0683c35
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Fixed a bug where skipping a sprite by modifying LCDC flags mid-scanline will disable sprites for the rest of the scalene.
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2018-04-05 00:51:37 +03:00 |
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Lior Halphon
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5d63892949
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T-cycle accurate timing of the extra OAM interrupt. Fixes vblank_stat_intr-GS, related to #54
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2018-04-03 01:43:24 +03:00 |
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Lior Halphon
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e163026ca9
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The STAT bug does not occur during the glitched mode 0
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2018-04-02 01:05:32 +03:00 |
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Lior Halphon
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9339a6027f
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Slight refinement to the last fix
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2018-04-01 22:20:26 +03:00 |
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Lior Halphon
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ec64c041ab
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The OAM interrupt is internally implemented differently from the other 3. Fixed the stat_write_if tests, relates to #54
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2018-04-01 21:45:56 +03:00 |
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Lior Halphon
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73dc3560a5
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Mode 0 interrupts do not occur in the glitched mode 0 of the first line 0. The extra OAM interrupt bug also affects DMG.
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2018-03-31 13:18:02 +03:00 |
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Lior Halphon
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0a2d6e6dcb
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Fixed DMG timing regression
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2018-03-31 12:21:34 +03:00 |
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Lior Halphon
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9811dceca1
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Emulate another OAM timing quirk; a sprite at x = 0 has extra penalty if SCX is not 0. Fixes intr_2_mode0_timing_sprites_scx*_nops, affects #54
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2018-03-30 17:06:27 +03:00 |
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Lior Halphon
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2c44ffbe39
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More accurate fetcher penalty emulation, fixed intr_2_mode0_timing_sprites_nops, affects #54
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2018-03-30 02:53:49 +03:00 |
|
Kyle Swanson
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7bfe5de9c7
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chmod -x
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2018-03-28 21:37:34 -07:00 |
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Lior Halphon
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0e3d2770d9
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Properly handle cases where an object’s X position is modified between the OAM mode and rendering mode
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2018-03-27 22:13:08 +03:00 |
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Lior Halphon
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4986930511
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Mostly complete emulation of the OAM bug. Passes oam_bug-2.
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2018-03-27 15:46:00 +03:00 |
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Lior Halphon
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5cb74fb684
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Bugfix: turning the PPU off during OAM mode made the OAM bug persist while the LCD is off
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2018-03-24 02:58:37 +03:00 |
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Lior Halphon
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4e3928df81
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Turns out the behavior differs between DMG and CGB – in DMG mode, the objects enabled bit is checked before halting the FIFOs, meaning that disabled sprites do not affect Mode 3’s length on the DMG.
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2018-03-23 20:01:27 +03:00 |
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Lior Halphon
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48a8db233d
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Refinement to the last fix
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2018-03-23 19:54:11 +03:00 |
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Lior Halphon
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e9eeace995
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The object enabled bit is checked only when popping from the object FIFO. Objects affect timing even when disabled.
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2018-03-23 19:50:19 +03:00 |
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Lior Halphon
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04bfc89816
|
Cycle accurate OAM search mode
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2018-03-23 19:07:14 +03:00 |
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Lior Halphon
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c11af7ea26
|
Fix CGB timings
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2018-03-23 12:58:51 +03:00 |
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Lior Halphon
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e9f243a913
|
Fix sprite priority
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2018-03-21 00:02:35 +02:00 |
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Lior Halphon
|
cb33a5b25a
|
Fix Aevilla
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2018-03-20 20:08:29 +02:00 |
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Lior Halphon
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3883b7d86a
|
Merge branch 'master' into timing
# Conflicts:
# Core/display.c
# Core/z80_cpu.c
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2018-03-19 23:46:33 +02:00 |
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Lior Halphon
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b50c97f4a7
|
Prevent starting HDMA in the middle of an instruction, making both the CPU and DMA access memory at the same time. Closes #47
|
2018-03-19 20:01:31 +02:00 |
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Lior Halphon
|
202eb2b5cc
|
Fix stat_lyc_onoff
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2018-03-18 20:32:19 +02:00 |
|
Lior Halphon
|
80b1275e07
|
Fix stat_lyc_onoff
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2018-03-18 20:08:45 +02:00 |
|
Lior Halphon
|
12ae5745db
|
While fixing some rendering issues, this change was incorrect.
|
2018-03-17 21:04:48 +02:00 |
|
Lior Halphon
|
269bac4626
|
More CGB fixes
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2018-03-17 20:34:55 +02:00 |
|
Lior Halphon
|
21b75494a2
|
More CGB fixes (currently on DMG-mode CGB is verified). Halt interrupt timing isn’t correct yet.
|
2018-03-11 00:17:57 +02:00 |
|
Lior Halphon
|
15b6c48d7c
|
Fixed vblank_stat_intr-C
|
2018-03-10 15:52:22 +02:00 |
|
Lior Halphon
|
c267ad00b5
|
Goodbye
|
2018-03-09 23:34:23 +02:00 |
|
Lior Halphon
|
e8b107efdb
|
In double speed mode, there are no quirks where IF and STAT don’t update together
|
2018-03-09 23:31:49 +02:00 |
|
Lior Halphon
|
cb6bb0590e
|
Starting to fix CGB timing quirks
|
2018-03-09 21:11:35 +02:00 |
|
Lior Halphon
|
9083e883fe
|
CGB BG rendering
|
2018-03-09 18:52:36 +02:00 |
|
Lior Halphon
|
a32f232bb1
|
Fixed OAM-window priority glitch, fixed OAM glitch in Prehistoric Man
|
2018-03-09 17:10:19 +02:00 |