Lior Halphon
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11c148c851
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Starting G/HDMA directly takes one more M-cycle (More research required)
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2018-09-15 00:48:31 +03:00 |
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Lior Halphon
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dbc338a887
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Compensate for prefetch in DIV’s initial value
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2018-09-15 00:47:26 +03:00 |
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Lior Halphon
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ec0a879a93
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Correct emulation of enabling and disabling the volume envelope. Correct emulation of a glitch where the volume envelope ticks when it usually wouldn’t.
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2018-09-10 16:59:59 +03:00 |
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Lior Halphon
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3151821e6d
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Fixed minor APU regression (Channels 1 and 2 were given no delay under certain circumstances)
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2018-09-09 12:50:55 +03:00 |
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a36dd791ec
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Rewrite the DAA instruction
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2018-07-22 18:37:34 +02:00 |
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Lior Halphon
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f7b882f0e8
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Whoops
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2018-07-22 02:10:26 +03:00 |
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Lior Halphon
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b7426f93c0
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Randomize object palettes. Slightly more accurate emulation of FF4C.
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2018-07-20 23:23:47 +03:00 |
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Lior Halphon
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ce80acc818
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Fixed HDMA timing )But still not verified)
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2018-07-20 12:34:52 +03:00 |
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Lior Halphon
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b1cc55b786
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Turns out Left/Right audio channels were flipped
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2018-07-19 20:38:11 +03:00 |
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Lior Halphon
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c66b6fbafc
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Fixed an edge case with DAC discharge emulation
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2018-07-16 23:08:25 +03:00 |
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Lior Halphon
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2e9e3424ec
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Document some revision differences
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2018-07-14 21:52:54 +03:00 |
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Lior Halphon
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0145b790a3
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Merge branch 'v0.11.x'
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2018-07-11 20:08:33 +03:00 |
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Lior Halphon
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5f58323c01
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Attempt to improve audio quality on frontend with big audio buffers
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2018-07-10 21:33:03 +03:00 |
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Lior Halphon
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dc5cb71c22
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Emulate CGB-C’s quirky LFSR function
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2018-07-04 21:55:12 +03:00 |
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Lior Halphon
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f3437d7cc0
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Added todo
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2018-07-03 23:47:50 +03:00 |
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Lior Halphon
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b7b35c9b59
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CGB-C timing
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2018-07-03 22:25:09 +03:00 |
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Lior Halphon
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0a78f735d3
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Fetcher Y is not cached on CGB-C
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2018-07-03 22:14:53 +03:00 |
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Lior Halphon
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18ae18a95c
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LYC bit on CGB-C
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2018-07-03 21:56:32 +03:00 |
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Lior Halphon
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a7aabca618
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Starting to add CGB-C support
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2018-07-03 21:43:46 +03:00 |
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Lior Halphon
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47a74cb6c3
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Randomize initial RAM values. Closes #82
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2018-06-30 16:53:28 +03:00 |
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Lior Halphon
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2791775c5d
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Improvements to the lcd debugger command
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2018-06-22 18:38:54 +03:00 |
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Lior Halphon
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6a7c084177
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Fixed window regression
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2018-06-18 21:57:01 +03:00 |
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Lior Halphon
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d81c23cb16
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Fixed HDMA regression
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2018-06-16 23:52:24 +03:00 |
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Lior Halphon
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45c73e0175
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Replaced the is_cgb bool with a more future compatible model enum. Removed the GB_init_cgb API and replaced it with an extended GB_init and GB_switch_model_and_reset APIs that now receive a model parameter. Increased the struct version.
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2018-06-16 13:59:33 +03:00 |
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Lior Halphon
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d95ad1ca54
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SWAP was incorrectly disassembled as RLC
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2018-06-09 15:39:40 +03:00 |
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Lior Halphon
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38c0cb3323
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Typo
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2018-06-09 15:12:42 +03:00 |
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Lior Halphon
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f64da1864f
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APU glitch: When turning the APU on while DIV's bit 4 (or 5 in double speed mode), the first DIV/APU event is skipped.
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2018-06-09 15:11:20 +03:00 |
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Lior Halphon
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593cb7c107
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Pixel accurate emulation of Prehistorik Man on a CGB-CPU-E
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2018-06-08 18:44:03 +03:00 |
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Lior Halphon
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ca01ff6f79
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Finally, perfect emulation of the STAT write bug.
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2018-06-08 17:16:15 +03:00 |
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Lior Halphon
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127324d2d6
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Fixed regression involving rendering a window with negative X position. Closes #75
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2018-06-07 23:08:46 +03:00 |
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Lior Halphon
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f1dfa2a1bc
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More sensible implementation of the STAT interrupt.
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2018-06-04 02:07:38 +03:00 |
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Lior Halphon
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0481ff9af5
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Whoops
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2018-06-04 01:52:24 +03:00 |
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Lior Halphon
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8721a48206
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Fixed incorrect double speed behavior.
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2018-06-03 00:36:05 +03:00 |
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Lior Halphon
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7003e31b7e
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Fixed a regression with STAT blocking.
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2018-06-02 04:00:10 +03:00 |
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Lior Halphon
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80c92daacd
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Include cleanup (#73)
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2018-05-27 19:30:23 +03:00 |
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Lior Halphon
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6532aef089
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Correct emulation of the DMG stat write bug
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2018-05-26 18:06:40 +03:00 |
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Lior Halphon
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9693b2de6a
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Refined the STAT bug behavior. Still not perfect.
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2018-05-26 17:06:49 +03:00 |
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Lior Halphon
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855ffb490a
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A HBlank interrupt cannot occur in the last M-cycle of HBlank. Correct emulation of STAT access conflicts on the CGB (Test: CPU-E, single speed only). Fixes a minor graphical glitch in Pokémon Puzzle Challenge.
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2018-05-25 23:42:36 +03:00 |
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Lior Halphon
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249acb04cc
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Verified some timings on a DMG. Fixed palette write conflict timing (Although the fix kind of implies time traveling). Closes #65
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2018-05-16 00:59:11 +03:00 |
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Lior Halphon
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562b43a7c5
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Notes about the DMG wave-ram glitch
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2018-05-15 23:02:07 +03:00 |
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Lior Halphon
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7df571d42f
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Less strict matching for delete and unwatch. Fixes #71
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2018-05-13 23:17:23 +03:00 |
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Lior Halphon
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1fcde88d8a
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Improved accuracy of the halt bug
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2018-05-12 22:13:52 +03:00 |
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Lior Halphon
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713dc02e46
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A bit tacky, but T-cycle accurate emulation of LYC write conflicts on the CGB. Only single speed mode verified. Closes #54
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2018-05-11 12:38:55 +03:00 |
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Lior Halphon
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af3554c1d1
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More accurate emulation of the LYC register and interrupt. (Still not perfect on a CGB)
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2018-04-27 13:40:39 +03:00 |
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Lior Halphon
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0f8385a798
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Refined line 153 behavior on a CGB. Verified on CGB-E.
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2018-04-25 00:08:06 +03:00 |
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Lior Halphon
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be9df4d658
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Added mechanism to handle MMIO read/write conflicts. Fixes #65
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2018-04-14 17:57:00 +03:00 |
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Lior Halphon
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2c6f7906c5
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Make multi-byte opcodes trigger the OAM bug when they increase PC
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2018-04-14 15:32:55 +03:00 |
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Lior Halphon
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84aa06aba5
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Clean up OAM bug code
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2018-04-14 13:35:16 +03:00 |
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Lior Halphon
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d667d87bbe
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Refactor CPU code so handling access conflicts is possible
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2018-04-14 13:25:55 +03:00 |
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Lior Halphon
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f1ec42d4ba
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H/GDMA was 4 times faster than it should have been. Made it also more accurate. Fixes #56
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2018-04-13 14:41:39 +03:00 |
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