Lior Halphon
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d95ad1ca54
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SWAP was incorrectly disassembled as RLC
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2018-06-09 15:39:40 +03:00 |
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Lior Halphon
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38c0cb3323
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Typo
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2018-06-09 15:12:42 +03:00 |
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Lior Halphon
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f64da1864f
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APU glitch: When turning the APU on while DIV's bit 4 (or 5 in double speed mode), the first DIV/APU event is skipped.
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2018-06-09 15:11:20 +03:00 |
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Lior Halphon
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593cb7c107
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Pixel accurate emulation of Prehistorik Man on a CGB-CPU-E
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2018-06-08 18:44:03 +03:00 |
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Lior Halphon
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ca01ff6f79
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Finally, perfect emulation of the STAT write bug.
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2018-06-08 17:16:15 +03:00 |
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Lior Halphon
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127324d2d6
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Fixed regression involving rendering a window with negative X position. Closes #75
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2018-06-07 23:08:46 +03:00 |
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Lior Halphon
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f1dfa2a1bc
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More sensible implementation of the STAT interrupt.
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2018-06-04 02:07:38 +03:00 |
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Lior Halphon
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0481ff9af5
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Whoops
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2018-06-04 01:52:24 +03:00 |
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Lior Halphon
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8721a48206
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Fixed incorrect double speed behavior.
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2018-06-03 00:36:05 +03:00 |
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Lior Halphon
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7003e31b7e
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Fixed a regression with STAT blocking.
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2018-06-02 04:00:10 +03:00 |
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Lior Halphon
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80c92daacd
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Include cleanup (#73)
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2018-05-27 19:30:23 +03:00 |
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Lior Halphon
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6532aef089
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Correct emulation of the DMG stat write bug
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2018-05-26 18:06:40 +03:00 |
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Lior Halphon
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9693b2de6a
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Refined the STAT bug behavior. Still not perfect.
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2018-05-26 17:06:49 +03:00 |
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Lior Halphon
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855ffb490a
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A HBlank interrupt cannot occur in the last M-cycle of HBlank. Correct emulation of STAT access conflicts on the CGB (Test: CPU-E, single speed only). Fixes a minor graphical glitch in Pokémon Puzzle Challenge.
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2018-05-25 23:42:36 +03:00 |
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Lior Halphon
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249acb04cc
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Verified some timings on a DMG. Fixed palette write conflict timing (Although the fix kind of implies time traveling). Closes #65
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2018-05-16 00:59:11 +03:00 |
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Lior Halphon
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562b43a7c5
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Notes about the DMG wave-ram glitch
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2018-05-15 23:02:07 +03:00 |
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Lior Halphon
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7df571d42f
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Less strict matching for `delete` and `unwatch`. Fixes #71
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2018-05-13 23:17:23 +03:00 |
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Lior Halphon
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1fcde88d8a
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Improved accuracy of the halt bug
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2018-05-12 22:13:52 +03:00 |
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Lior Halphon
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713dc02e46
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A bit tacky, but T-cycle accurate emulation of LYC write conflicts on the CGB. Only single speed mode verified. Closes #54
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2018-05-11 12:38:55 +03:00 |
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Lior Halphon
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af3554c1d1
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More accurate emulation of the LYC register and interrupt. (Still not perfect on a CGB)
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2018-04-27 13:40:39 +03:00 |
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Lior Halphon
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0f8385a798
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Refined line 153 behavior on a CGB. Verified on CGB-E.
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2018-04-25 00:08:06 +03:00 |
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Lior Halphon
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be9df4d658
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Added mechanism to handle MMIO read/write conflicts. Fixes #65
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2018-04-14 17:57:00 +03:00 |
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Lior Halphon
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2c6f7906c5
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Make multi-byte opcodes trigger the OAM bug when they increase PC
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2018-04-14 15:32:55 +03:00 |
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Lior Halphon
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84aa06aba5
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Clean up OAM bug code
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2018-04-14 13:35:16 +03:00 |
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Lior Halphon
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d667d87bbe
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Refactor CPU code so handling access conflicts is possible
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2018-04-14 13:25:55 +03:00 |
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Lior Halphon
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f1ec42d4ba
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H/GDMA was 4 times faster than it should have been. Made it also more accurate. Fixes #56
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2018-04-13 14:41:39 +03:00 |
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orbea
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10dc12c502
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Core: Fix libretro builds
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2018-04-11 14:21:46 -07:00 |
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Lior Halphon
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89094950f8
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Correct emulation of mapping both button sets. Fixes #60
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2018-04-07 16:45:31 +03:00 |
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Lior Halphon
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5be2b3db29
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It appears that OAM DMA blocks PPU access to OAM
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2018-04-07 13:59:36 +03:00 |
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Lior Halphon
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0725b008be
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Further simplifications
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2018-04-07 13:02:53 +03:00 |
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Lior Halphon
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097b768127
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Update comments
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2018-04-07 03:36:47 +03:00 |
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Lior Halphon
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9ce028056a
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Cleanup
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2018-04-07 03:26:10 +03:00 |
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Lior Halphon
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fed2556fc3
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More reasonable implementation of sprite timings
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2018-04-07 03:00:26 +03:00 |
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Lior Halphon
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0751eae90b
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Moved the fetcher state machine to another function
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2018-04-06 19:29:49 +03:00 |
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Lior Halphon
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0461fb5b2a
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Simplified FIFO logic
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2018-04-06 19:11:48 +03:00 |
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Lior Halphon
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cb01259073
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Fixed #61
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2018-04-06 11:37:49 +03:00 |
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Lior Halphon
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0c86ff1ee4
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More CGB revision quirks
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2018-04-06 04:00:37 +03:00 |
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Lior Halphon
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a6ed2029b7
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New information about PPU changes between CGB-B and CGB-E
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2018-04-06 03:19:47 +03:00 |
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Lior Halphon
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cc95c89d3c
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Surprise! The CGB has a 16-bit VRAM data bus
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2018-04-05 16:15:51 +03:00 |
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Lior Halphon
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9aadc80f75
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Implemented some obscure PPU rendering quirks, verified some timings
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2018-04-05 15:33:21 +03:00 |
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Lior Halphon
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d785e45308
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More accurate emulation of LCDC.0
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2018-04-05 12:27:01 +03:00 |
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Lior Halphon
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d8e0683c35
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Fixed a bug where skipping a sprite by modifying LCDC flags mid-scanline will disable sprites for the rest of the scalene.
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2018-04-05 00:51:37 +03:00 |
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Lior Halphon
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5d63892949
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T-cycle accurate timing of the extra OAM interrupt. Fixes vblank_stat_intr-GS, related to #54
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2018-04-03 01:43:24 +03:00 |
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Lior Halphon
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ba07e7ba85
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Fixed a bug where 0:$dxxx reads/writes from the wrong bank in CGB mode. Made sure symbols are reset after reloading a sym file.
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2018-04-02 19:57:39 +03:00 |
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Lior Halphon
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e163026ca9
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The STAT bug does not occur during the glitched mode 0
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2018-04-02 01:05:32 +03:00 |
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Lior Halphon
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9339a6027f
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Slight refinement to the last fix
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2018-04-01 22:20:26 +03:00 |
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Lior Halphon
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ec64c041ab
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The OAM interrupt is internally implemented differently from the other 3. Fixed the stat_write_if tests, relates to #54
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2018-04-01 21:45:56 +03:00 |
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Lior Halphon
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0d0d9ccdae
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Fixed a timer regression, fixes timer_if in DMG mode. Relates to #54
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2018-03-31 15:52:31 +03:00 |
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Lior Halphon
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73dc3560a5
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Mode 0 interrupts do not occur in the glitched mode 0 of the first line 0. The extra OAM interrupt bug also affects DMG.
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2018-03-31 13:18:02 +03:00 |
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Lior Halphon
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0a2d6e6dcb
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Fixed DMG timing regression
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2018-03-31 12:21:34 +03:00 |