Lior Halphon
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431f1f8199
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Remove redundant calls to display_vblank on non-SGB models and in irregular FPS scenarios. Affects #161
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2019-06-18 23:16:28 +03:00 |
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Lior Halphon
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0da2930109
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Fix #175
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2019-06-08 14:35:52 +03:00 |
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Lior Halphon
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64879f5b02
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Accurate emulation of (most aspects of) stop mode
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2019-06-07 13:53:50 +03:00 |
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Lior Halphon
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06670fc970
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Fix #172. Allow unroll optimizations when compiling with GCC.
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2019-05-10 21:51:11 +03:00 |
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orbea
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2bded45397
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Disable pragmas for gcc.
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2019-05-09 10:55:31 -07:00 |
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Lior Halphon
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7242ddae64
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speling is difikult
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2019-03-16 20:56:22 +02:00 |
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Lior Halphon
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0b03b61564
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Render the first line 0, as required for SGB emulation
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2019-02-16 04:19:16 +02:00 |
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Lior Halphon
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9d0aadb83f
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Emulate missing Vreset signal (SGB only for now) and ICD2 desyncing
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2019-02-15 17:04:48 +02:00 |
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Lior Halphon
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73a54049d2
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Accurate PPU access timings
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2019-01-19 19:32:26 +02:00 |
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Lior Halphon
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7b36ee10a4
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Merge branch 'master' into sgb
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2019-01-05 19:00:22 +02:00 |
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Lior Halphon
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af0430dbc5
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Unroll some loops in PPU code, more efficient timer handling
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2018-12-31 22:06:20 +02:00 |
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Lior Halphon
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398148f7ea
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Basic SGB border support
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2018-11-16 16:04:40 +02:00 |
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Lior Halphon
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2f2b792edf
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SGB save states
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2018-11-16 01:53:01 +02:00 |
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Lior Halphon
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634a54c046
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SGB resolution support (Cocoa only so far)
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2018-11-15 00:21:21 +02:00 |
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Lior Halphon
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ce80acc818
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Fixed HDMA timing )But still not verified)
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2018-07-20 12:34:52 +03:00 |
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Lior Halphon
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b7b35c9b59
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CGB-C timing
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2018-07-03 22:25:09 +03:00 |
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Lior Halphon
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0a78f735d3
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Fetcher Y is not cached on CGB-C
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2018-07-03 22:14:53 +03:00 |
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Lior Halphon
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18ae18a95c
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LYC bit on CGB-C
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2018-07-03 21:56:32 +03:00 |
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Lior Halphon
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6a7c084177
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Fixed window regression
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2018-06-18 21:57:01 +03:00 |
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Lior Halphon
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45c73e0175
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Replaced the is_cgb bool with a more future compatible model enum. Removed the GB_init_cgb API and replaced it with an extended GB_init and GB_switch_model_and_reset APIs that now receive a model parameter. Increased the struct version.
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2018-06-16 13:59:33 +03:00 |
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Lior Halphon
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ca01ff6f79
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Finally, perfect emulation of the STAT write bug.
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2018-06-08 17:16:15 +03:00 |
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Lior Halphon
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127324d2d6
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Fixed regression involving rendering a window with negative X position. Closes #75
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2018-06-07 23:08:46 +03:00 |
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Lior Halphon
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f1dfa2a1bc
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More sensible implementation of the STAT interrupt.
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2018-06-04 02:07:38 +03:00 |
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Lior Halphon
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8721a48206
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Fixed incorrect double speed behavior.
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2018-06-03 00:36:05 +03:00 |
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Lior Halphon
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7003e31b7e
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Fixed a regression with STAT blocking.
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2018-06-02 04:00:10 +03:00 |
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Lior Halphon
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9693b2de6a
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Refined the STAT bug behavior. Still not perfect.
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2018-05-26 17:06:49 +03:00 |
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Lior Halphon
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855ffb490a
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A HBlank interrupt cannot occur in the last M-cycle of HBlank. Correct emulation of STAT access conflicts on the CGB (Test: CPU-E, single speed only). Fixes a minor graphical glitch in Pokémon Puzzle Challenge.
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2018-05-25 23:42:36 +03:00 |
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Lior Halphon
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713dc02e46
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A bit tacky, but T-cycle accurate emulation of LYC write conflicts on the CGB. Only single speed mode verified. Closes #54
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2018-05-11 12:38:55 +03:00 |
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Lior Halphon
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af3554c1d1
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More accurate emulation of the LYC register and interrupt. (Still not perfect on a CGB)
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2018-04-27 13:40:39 +03:00 |
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Lior Halphon
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0f8385a798
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Refined line 153 behavior on a CGB. Verified on CGB-E.
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2018-04-25 00:08:06 +03:00 |
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Lior Halphon
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5be2b3db29
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It appears that OAM DMA blocks PPU access to OAM
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2018-04-07 13:59:36 +03:00 |
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Lior Halphon
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0725b008be
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Further simplifications
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2018-04-07 13:02:53 +03:00 |
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Lior Halphon
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097b768127
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Update comments
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2018-04-07 03:36:47 +03:00 |
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Lior Halphon
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9ce028056a
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Cleanup
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2018-04-07 03:26:10 +03:00 |
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Lior Halphon
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fed2556fc3
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More reasonable implementation of sprite timings
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2018-04-07 03:00:26 +03:00 |
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Lior Halphon
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0751eae90b
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Moved the fetcher state machine to another function
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2018-04-06 19:29:49 +03:00 |
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Lior Halphon
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0461fb5b2a
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Simplified FIFO logic
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2018-04-06 19:11:48 +03:00 |
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Lior Halphon
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cb01259073
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Fixed #61
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2018-04-06 11:37:49 +03:00 |
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Lior Halphon
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a6ed2029b7
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New information about PPU changes between CGB-B and CGB-E
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2018-04-06 03:19:47 +03:00 |
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Lior Halphon
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cc95c89d3c
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Surprise! The CGB has a 16-bit VRAM data bus
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2018-04-05 16:15:51 +03:00 |
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Lior Halphon
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9aadc80f75
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Implemented some obscure PPU rendering quirks, verified some timings
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2018-04-05 15:33:21 +03:00 |
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Lior Halphon
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d785e45308
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More accurate emulation of LCDC.0
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2018-04-05 12:27:01 +03:00 |
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Lior Halphon
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d8e0683c35
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Fixed a bug where skipping a sprite by modifying LCDC flags mid-scanline will disable sprites for the rest of the scalene.
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2018-04-05 00:51:37 +03:00 |
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Lior Halphon
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5d63892949
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T-cycle accurate timing of the extra OAM interrupt. Fixes vblank_stat_intr-GS, related to #54
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2018-04-03 01:43:24 +03:00 |
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Lior Halphon
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e163026ca9
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The STAT bug does not occur during the glitched mode 0
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2018-04-02 01:05:32 +03:00 |
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Lior Halphon
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9339a6027f
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Slight refinement to the last fix
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2018-04-01 22:20:26 +03:00 |
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Lior Halphon
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ec64c041ab
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The OAM interrupt is internally implemented differently from the other 3. Fixed the stat_write_if tests, relates to #54
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2018-04-01 21:45:56 +03:00 |
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Lior Halphon
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73dc3560a5
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Mode 0 interrupts do not occur in the glitched mode 0 of the first line 0. The extra OAM interrupt bug also affects DMG.
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2018-03-31 13:18:02 +03:00 |
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Lior Halphon
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0a2d6e6dcb
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Fixed DMG timing regression
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2018-03-31 12:21:34 +03:00 |
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Lior Halphon
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9811dceca1
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Emulate another OAM timing quirk; a sprite at x = 0 has extra penalty if SCX is not 0. Fixes intr_2_mode0_timing_sprites_scx*_nops, affects #54
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2018-03-30 17:06:27 +03:00 |
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