Lior Halphon
|
06670fc970
|
Fix #172. Allow unroll optimizations when compiling with GCC.
|
2019-05-10 21:51:11 +03:00 |
|
orbea
|
2bded45397
|
Disable pragmas for gcc.
|
2019-05-09 10:55:31 -07:00 |
|
Lior Halphon
|
7242ddae64
|
speling is difikult
|
2019-03-16 20:56:22 +02:00 |
|
Lior Halphon
|
0b03b61564
|
Render the first line 0, as required for SGB emulation
|
2019-02-16 04:19:16 +02:00 |
|
Lior Halphon
|
9d0aadb83f
|
Emulate missing Vreset signal (SGB only for now) and ICD2 desyncing
|
2019-02-15 17:04:48 +02:00 |
|
Lior Halphon
|
73a54049d2
|
Accurate PPU access timings
|
2019-01-19 19:32:26 +02:00 |
|
Lior Halphon
|
7b36ee10a4
|
Merge branch 'master' into sgb
|
2019-01-05 19:00:22 +02:00 |
|
Lior Halphon
|
af0430dbc5
|
Unroll some loops in PPU code, more efficient timer handling
|
2018-12-31 22:06:20 +02:00 |
|
Lior Halphon
|
398148f7ea
|
Basic SGB border support
|
2018-11-16 16:04:40 +02:00 |
|
Lior Halphon
|
2f2b792edf
|
SGB save states
|
2018-11-16 01:53:01 +02:00 |
|
Lior Halphon
|
634a54c046
|
SGB resolution support (Cocoa only so far)
|
2018-11-15 00:21:21 +02:00 |
|
Lior Halphon
|
ce80acc818
|
Fixed HDMA timing )But still not verified)
|
2018-07-20 12:34:52 +03:00 |
|
Lior Halphon
|
b7b35c9b59
|
CGB-C timing
|
2018-07-03 22:25:09 +03:00 |
|
Lior Halphon
|
0a78f735d3
|
Fetcher Y is not cached on CGB-C
|
2018-07-03 22:14:53 +03:00 |
|
Lior Halphon
|
18ae18a95c
|
LYC bit on CGB-C
|
2018-07-03 21:56:32 +03:00 |
|
Lior Halphon
|
6a7c084177
|
Fixed window regression
|
2018-06-18 21:57:01 +03:00 |
|
Lior Halphon
|
45c73e0175
|
Replaced the is_cgb bool with a more future compatible model enum. Removed the GB_init_cgb API and replaced it with an extended GB_init and GB_switch_model_and_reset APIs that now receive a model parameter. Increased the struct version.
|
2018-06-16 13:59:33 +03:00 |
|
Lior Halphon
|
ca01ff6f79
|
Finally, perfect emulation of the STAT write bug.
|
2018-06-08 17:16:15 +03:00 |
|
Lior Halphon
|
127324d2d6
|
Fixed regression involving rendering a window with negative X position. Closes #75
|
2018-06-07 23:08:46 +03:00 |
|
Lior Halphon
|
f1dfa2a1bc
|
More sensible implementation of the STAT interrupt.
|
2018-06-04 02:07:38 +03:00 |
|
Lior Halphon
|
8721a48206
|
Fixed incorrect double speed behavior.
|
2018-06-03 00:36:05 +03:00 |
|
Lior Halphon
|
7003e31b7e
|
Fixed a regression with STAT blocking.
|
2018-06-02 04:00:10 +03:00 |
|
Lior Halphon
|
9693b2de6a
|
Refined the STAT bug behavior. Still not perfect.
|
2018-05-26 17:06:49 +03:00 |
|
Lior Halphon
|
855ffb490a
|
A HBlank interrupt cannot occur in the last M-cycle of HBlank. Correct emulation of STAT access conflicts on the CGB (Test: CPU-E, single speed only). Fixes a minor graphical glitch in Pokémon Puzzle Challenge.
|
2018-05-25 23:42:36 +03:00 |
|
Lior Halphon
|
713dc02e46
|
A bit tacky, but T-cycle accurate emulation of LYC write conflicts on the CGB. Only single speed mode verified. Closes #54
|
2018-05-11 12:38:55 +03:00 |
|
Lior Halphon
|
af3554c1d1
|
More accurate emulation of the LYC register and interrupt. (Still not perfect on a CGB)
|
2018-04-27 13:40:39 +03:00 |
|
Lior Halphon
|
0f8385a798
|
Refined line 153 behavior on a CGB. Verified on CGB-E.
|
2018-04-25 00:08:06 +03:00 |
|
Lior Halphon
|
5be2b3db29
|
It appears that OAM DMA blocks PPU access to OAM
|
2018-04-07 13:59:36 +03:00 |
|
Lior Halphon
|
0725b008be
|
Further simplifications
|
2018-04-07 13:02:53 +03:00 |
|
Lior Halphon
|
097b768127
|
Update comments
|
2018-04-07 03:36:47 +03:00 |
|
Lior Halphon
|
9ce028056a
|
Cleanup
|
2018-04-07 03:26:10 +03:00 |
|
Lior Halphon
|
fed2556fc3
|
More reasonable implementation of sprite timings
|
2018-04-07 03:00:26 +03:00 |
|
Lior Halphon
|
0751eae90b
|
Moved the fetcher state machine to another function
|
2018-04-06 19:29:49 +03:00 |
|
Lior Halphon
|
0461fb5b2a
|
Simplified FIFO logic
|
2018-04-06 19:11:48 +03:00 |
|
Lior Halphon
|
cb01259073
|
Fixed #61
|
2018-04-06 11:37:49 +03:00 |
|
Lior Halphon
|
a6ed2029b7
|
New information about PPU changes between CGB-B and CGB-E
|
2018-04-06 03:19:47 +03:00 |
|
Lior Halphon
|
cc95c89d3c
|
Surprise! The CGB has a 16-bit VRAM data bus
|
2018-04-05 16:15:51 +03:00 |
|
Lior Halphon
|
9aadc80f75
|
Implemented some obscure PPU rendering quirks, verified some timings
|
2018-04-05 15:33:21 +03:00 |
|
Lior Halphon
|
d785e45308
|
More accurate emulation of LCDC.0
|
2018-04-05 12:27:01 +03:00 |
|
Lior Halphon
|
d8e0683c35
|
Fixed a bug where skipping a sprite by modifying LCDC flags mid-scanline will disable sprites for the rest of the scalene.
|
2018-04-05 00:51:37 +03:00 |
|
Lior Halphon
|
5d63892949
|
T-cycle accurate timing of the extra OAM interrupt. Fixes vblank_stat_intr-GS, related to #54
|
2018-04-03 01:43:24 +03:00 |
|
Lior Halphon
|
e163026ca9
|
The STAT bug does not occur during the glitched mode 0
|
2018-04-02 01:05:32 +03:00 |
|
Lior Halphon
|
9339a6027f
|
Slight refinement to the last fix
|
2018-04-01 22:20:26 +03:00 |
|
Lior Halphon
|
ec64c041ab
|
The OAM interrupt is internally implemented differently from the other 3. Fixed the stat_write_if tests, relates to #54
|
2018-04-01 21:45:56 +03:00 |
|
Lior Halphon
|
73dc3560a5
|
Mode 0 interrupts do not occur in the glitched mode 0 of the first line 0. The extra OAM interrupt bug also affects DMG.
|
2018-03-31 13:18:02 +03:00 |
|
Lior Halphon
|
0a2d6e6dcb
|
Fixed DMG timing regression
|
2018-03-31 12:21:34 +03:00 |
|
Lior Halphon
|
9811dceca1
|
Emulate another OAM timing quirk; a sprite at x = 0 has extra penalty if SCX is not 0. Fixes intr_2_mode0_timing_sprites_scx*_nops, affects #54
|
2018-03-30 17:06:27 +03:00 |
|
Lior Halphon
|
2c44ffbe39
|
More accurate fetcher penalty emulation, fixed intr_2_mode0_timing_sprites_nops, affects #54
|
2018-03-30 02:53:49 +03:00 |
|
Kyle Swanson
|
7bfe5de9c7
|
chmod -x
|
2018-03-28 21:37:34 -07:00 |
|
Lior Halphon
|
0e3d2770d9
|
Properly handle cases where an object’s X position is modified between the OAM mode and rendering mode
|
2018-03-27 22:13:08 +03:00 |
|