Lior Halphon
|
b7b35c9b59
|
CGB-C timing
|
2018-07-03 22:25:09 +03:00 |
|
Lior Halphon
|
0a78f735d3
|
Fetcher Y is not cached on CGB-C
|
2018-07-03 22:14:53 +03:00 |
|
Lior Halphon
|
18ae18a95c
|
LYC bit on CGB-C
|
2018-07-03 21:56:32 +03:00 |
|
Lior Halphon
|
a7aabca618
|
Starting to add CGB-C support
|
2018-07-03 21:43:46 +03:00 |
|
Lior Halphon
|
47a74cb6c3
|
Randomize initial RAM values. Closes #82
|
2018-06-30 16:53:28 +03:00 |
|
Lior Halphon
|
2791775c5d
|
Improvements to the lcd debugger command
|
2018-06-22 18:38:54 +03:00 |
|
Lior Halphon
|
6a7c084177
|
Fixed window regression
|
2018-06-18 21:57:01 +03:00 |
|
Lior Halphon
|
d81c23cb16
|
Fixed HDMA regression
|
2018-06-16 23:52:24 +03:00 |
|
Lior Halphon
|
45c73e0175
|
Replaced the is_cgb bool with a more future compatible model enum. Removed the GB_init_cgb API and replaced it with an extended GB_init and GB_switch_model_and_reset APIs that now receive a model parameter. Increased the struct version.
|
2018-06-16 13:59:33 +03:00 |
|
Lior Halphon
|
d95ad1ca54
|
SWAP was incorrectly disassembled as RLC
|
2018-06-09 15:39:40 +03:00 |
|
Lior Halphon
|
38c0cb3323
|
Typo
|
2018-06-09 15:12:42 +03:00 |
|
Lior Halphon
|
f64da1864f
|
APU glitch: When turning the APU on while DIV's bit 4 (or 5 in double speed mode), the first DIV/APU event is skipped.
|
2018-06-09 15:11:20 +03:00 |
|
Lior Halphon
|
593cb7c107
|
Pixel accurate emulation of Prehistorik Man on a CGB-CPU-E
|
2018-06-08 18:44:03 +03:00 |
|
Lior Halphon
|
ca01ff6f79
|
Finally, perfect emulation of the STAT write bug.
|
2018-06-08 17:16:15 +03:00 |
|
Lior Halphon
|
127324d2d6
|
Fixed regression involving rendering a window with negative X position. Closes #75
|
2018-06-07 23:08:46 +03:00 |
|
Lior Halphon
|
f1dfa2a1bc
|
More sensible implementation of the STAT interrupt.
|
2018-06-04 02:07:38 +03:00 |
|
Lior Halphon
|
0481ff9af5
|
Whoops
|
2018-06-04 01:52:24 +03:00 |
|
Lior Halphon
|
8721a48206
|
Fixed incorrect double speed behavior.
|
2018-06-03 00:36:05 +03:00 |
|
Lior Halphon
|
7003e31b7e
|
Fixed a regression with STAT blocking.
|
2018-06-02 04:00:10 +03:00 |
|
Lior Halphon
|
80c92daacd
|
Include cleanup (#73)
|
2018-05-27 19:30:23 +03:00 |
|
Lior Halphon
|
6532aef089
|
Correct emulation of the DMG stat write bug
|
2018-05-26 18:06:40 +03:00 |
|
Lior Halphon
|
9693b2de6a
|
Refined the STAT bug behavior. Still not perfect.
|
2018-05-26 17:06:49 +03:00 |
|
Lior Halphon
|
855ffb490a
|
A HBlank interrupt cannot occur in the last M-cycle of HBlank. Correct emulation of STAT access conflicts on the CGB (Test: CPU-E, single speed only). Fixes a minor graphical glitch in Pokémon Puzzle Challenge.
|
2018-05-25 23:42:36 +03:00 |
|
Lior Halphon
|
249acb04cc
|
Verified some timings on a DMG. Fixed palette write conflict timing (Although the fix kind of implies time traveling). Closes #65
|
2018-05-16 00:59:11 +03:00 |
|
Lior Halphon
|
562b43a7c5
|
Notes about the DMG wave-ram glitch
|
2018-05-15 23:02:07 +03:00 |
|
Lior Halphon
|
7df571d42f
|
Less strict matching for delete and unwatch. Fixes #71
|
2018-05-13 23:17:23 +03:00 |
|
Lior Halphon
|
1fcde88d8a
|
Improved accuracy of the halt bug
|
2018-05-12 22:13:52 +03:00 |
|
Lior Halphon
|
713dc02e46
|
A bit tacky, but T-cycle accurate emulation of LYC write conflicts on the CGB. Only single speed mode verified. Closes #54
|
2018-05-11 12:38:55 +03:00 |
|
Lior Halphon
|
af3554c1d1
|
More accurate emulation of the LYC register and interrupt. (Still not perfect on a CGB)
|
2018-04-27 13:40:39 +03:00 |
|
Lior Halphon
|
0f8385a798
|
Refined line 153 behavior on a CGB. Verified on CGB-E.
|
2018-04-25 00:08:06 +03:00 |
|
Lior Halphon
|
be9df4d658
|
Added mechanism to handle MMIO read/write conflicts. Fixes #65
|
2018-04-14 17:57:00 +03:00 |
|
Lior Halphon
|
2c6f7906c5
|
Make multi-byte opcodes trigger the OAM bug when they increase PC
|
2018-04-14 15:32:55 +03:00 |
|
Lior Halphon
|
84aa06aba5
|
Clean up OAM bug code
|
2018-04-14 13:35:16 +03:00 |
|
Lior Halphon
|
d667d87bbe
|
Refactor CPU code so handling access conflicts is possible
|
2018-04-14 13:25:55 +03:00 |
|
Lior Halphon
|
f1ec42d4ba
|
H/GDMA was 4 times faster than it should have been. Made it also more accurate. Fixes #56
|
2018-04-13 14:41:39 +03:00 |
|
orbea
|
10dc12c502
|
Core: Fix libretro builds
|
2018-04-11 14:21:46 -07:00 |
|
Lior Halphon
|
89094950f8
|
Correct emulation of mapping both button sets. Fixes #60
|
2018-04-07 16:45:31 +03:00 |
|
Lior Halphon
|
5be2b3db29
|
It appears that OAM DMA blocks PPU access to OAM
|
2018-04-07 13:59:36 +03:00 |
|
Lior Halphon
|
0725b008be
|
Further simplifications
|
2018-04-07 13:02:53 +03:00 |
|
Lior Halphon
|
097b768127
|
Update comments
|
2018-04-07 03:36:47 +03:00 |
|
Lior Halphon
|
9ce028056a
|
Cleanup
|
2018-04-07 03:26:10 +03:00 |
|
Lior Halphon
|
fed2556fc3
|
More reasonable implementation of sprite timings
|
2018-04-07 03:00:26 +03:00 |
|
Lior Halphon
|
0751eae90b
|
Moved the fetcher state machine to another function
|
2018-04-06 19:29:49 +03:00 |
|
Lior Halphon
|
0461fb5b2a
|
Simplified FIFO logic
|
2018-04-06 19:11:48 +03:00 |
|
Lior Halphon
|
cb01259073
|
Fixed #61
|
2018-04-06 11:37:49 +03:00 |
|
Lior Halphon
|
0c86ff1ee4
|
More CGB revision quirks
|
2018-04-06 04:00:37 +03:00 |
|
Lior Halphon
|
a6ed2029b7
|
New information about PPU changes between CGB-B and CGB-E
|
2018-04-06 03:19:47 +03:00 |
|
Lior Halphon
|
cc95c89d3c
|
Surprise! The CGB has a 16-bit VRAM data bus
|
2018-04-05 16:15:51 +03:00 |
|
Lior Halphon
|
9aadc80f75
|
Implemented some obscure PPU rendering quirks, verified some timings
|
2018-04-05 15:33:21 +03:00 |
|
Lior Halphon
|
d785e45308
|
More accurate emulation of LCDC.0
|
2018-04-05 12:27:01 +03:00 |
|