2016-03-30 20:07:55 +00:00
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#ifndef apu_h
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#define apu_h
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#include <stdbool.h>
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#include <stdint.h>
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2018-05-27 16:30:23 +00:00
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#include <stddef.h>
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2021-11-07 11:39:18 +00:00
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#include "defs.h"
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2017-07-21 15:24:28 +00:00
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#ifdef GB_INTERNAL
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2018-02-16 16:01:50 +00:00
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/* Speed = 1 / Length (in seconds) */
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2019-05-25 16:12:09 +00:00
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#define DAC_DECAY_SPEED 20000
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#define DAC_ATTACK_SPEED 20000
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2018-10-19 20:53:01 +00:00
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2018-02-16 16:01:50 +00:00
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2018-01-06 09:58:07 +00:00
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/* Divides nicely and never overflows with 4 channels and 8 (1-8) volume levels */
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2018-02-07 20:27:28 +00:00
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#ifdef WIIU
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2018-02-10 13:02:22 +00:00
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/* Todo: Remove this hack once https://github.com/libretro/RetroArch/issues/6252 is fixed*/
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2018-02-15 23:26:37 +00:00
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#define MAX_CH_AMP (0xFF0 / 2)
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2018-02-07 20:27:28 +00:00
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#else
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2018-02-15 23:26:37 +00:00
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#define MAX_CH_AMP 0xFF0
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2018-02-07 20:27:28 +00:00
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#endif
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2018-01-06 09:58:07 +00:00
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#define CH_STEP (MAX_CH_AMP/0xF/8)
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2017-07-21 15:24:28 +00:00
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#endif
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2016-03-30 20:07:55 +00:00
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2018-02-16 16:01:50 +00:00
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2017-08-02 18:14:23 +00:00
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/* APU ticks are 2MHz, triggered by an internal APU clock. */
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2016-03-30 20:07:55 +00:00
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2016-06-10 12:28:50 +00:00
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typedef struct
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{
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int16_t left;
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int16_t right;
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} GB_sample_t;
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2017-08-15 18:14:55 +00:00
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typedef struct
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{
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double left;
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double right;
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} GB_double_sample_t;
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2017-07-21 15:24:28 +00:00
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enum GB_CHANNELS {
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GB_SQUARE_1,
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GB_SQUARE_2,
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GB_WAVE,
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GB_NOISE,
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GB_N_CHANNELS
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};
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2016-03-30 20:07:55 +00:00
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2021-02-25 13:43:38 +00:00
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typedef struct
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{
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bool locked:1;
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bool clock:1; // Represents FOSY on channel 4
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unsigned padding:6;
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} GB_envelope_clock_t;
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2019-06-15 20:22:27 +00:00
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typedef void (*GB_sample_callback_t)(GB_gameboy_t *gb, GB_sample_t *sample);
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2016-03-30 20:07:55 +00:00
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typedef struct
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{
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2016-09-12 22:21:47 +00:00
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bool global_enable;
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2017-07-27 20:11:33 +00:00
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uint8_t apu_cycles;
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2019-05-15 10:39:08 +00:00
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2017-07-21 15:24:28 +00:00
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uint8_t samples[GB_N_CHANNELS];
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bool is_active[GB_N_CHANNELS];
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2019-05-15 10:39:08 +00:00
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2017-08-02 18:14:23 +00:00
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uint8_t div_divider; // The DIV register ticks the APU at 512Hz, but is then divided
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// once more to generate 128Hz and 64Hz clocks
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2019-05-15 10:39:08 +00:00
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2017-08-11 14:57:08 +00:00
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uint8_t lf_div; // The APU runs in 2MHz, but channels 1, 2 and 4 run in 1MHZ so we divide
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// need to divide the signal.
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2019-05-15 10:39:08 +00:00
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2017-07-27 20:11:33 +00:00
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uint8_t square_sweep_countdown; // In 128Hz
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2017-08-15 19:05:20 +00:00
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uint8_t square_sweep_calculate_countdown; // In 2 MHz
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2020-11-28 17:31:25 +00:00
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uint16_t sweep_length_addend;
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2020-02-27 17:11:10 +00:00
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uint16_t shadow_sweep_sample_length;
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2021-01-02 12:56:45 +00:00
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bool unshifted_sweep;
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2021-01-08 14:43:00 +00:00
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bool enable_zombie_calculate_stepping;
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2021-11-06 23:10:58 +00:00
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uint8_t channel_1_restart_hold;
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uint16_t channel1_completed_addend;
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2017-07-27 20:11:33 +00:00
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struct {
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2017-08-02 18:14:23 +00:00
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uint16_t pulse_length; // Reloaded from NRX1 (xorred), in 256Hz DIV ticks
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2017-07-27 20:11:33 +00:00
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uint8_t current_volume; // Reloaded from NRX2
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uint8_t volume_countdown; // Reloaded from NRX2
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2021-11-06 23:10:58 +00:00
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uint8_t current_sample_index;
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bool sample_surpressed;
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2019-05-15 10:39:08 +00:00
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2017-08-10 16:42:23 +00:00
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uint16_t sample_countdown; // in APU ticks (Reloaded from sample_length, xorred $7FF)
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2017-08-02 18:14:23 +00:00
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uint16_t sample_length; // From NRX3, NRX4, in APU ticks
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2017-07-27 20:11:33 +00:00
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bool length_enabled; // NRX4
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2021-11-06 23:10:58 +00:00
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GB_envelope_clock_t envelope_clock;
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2017-07-27 20:11:33 +00:00
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} square_channels[2];
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2019-05-15 10:39:08 +00:00
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2017-07-21 15:24:28 +00:00
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struct {
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bool enable; // NR30
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2017-08-02 18:14:23 +00:00
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uint16_t pulse_length; // Reloaded from NR31 (xorred), in 256Hz DIV ticks
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2017-07-21 15:24:28 +00:00
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uint8_t shift; // NR32
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uint16_t sample_length; // NR33, NR34, in APU ticks
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bool length_enabled; // NR34
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2019-05-15 10:39:08 +00:00
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2017-08-10 16:42:23 +00:00
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uint16_t sample_countdown; // in APU ticks (Reloaded from sample_length, xorred $7FF)
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2017-07-21 15:24:28 +00:00
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uint8_t current_sample_index;
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2021-10-16 23:06:33 +00:00
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uint8_t current_sample_byte; // Current sample byte.
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2017-07-21 15:24:28 +00:00
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bool wave_form_just_read;
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2021-11-06 23:10:58 +00:00
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bool pulsed;
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2021-12-19 17:27:01 +00:00
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uint8_t bugged_read_countdown;
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2017-07-21 15:24:28 +00:00
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} wave_channel;
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2019-05-15 10:39:08 +00:00
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2017-08-11 14:57:08 +00:00
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struct {
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uint16_t pulse_length; // Reloaded from NR41 (xorred), in 256Hz DIV ticks
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uint8_t current_volume; // Reloaded from NR42
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uint8_t volume_countdown; // Reloaded from NR42
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uint16_t lfsr;
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bool narrow;
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2019-05-15 10:39:08 +00:00
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2020-12-12 14:02:25 +00:00
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uint8_t counter_countdown; // Counts from 0-7 to 0 to tick counter (Scaled from 512KHz to 2MHz)
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uint16_t counter; // A bit from this 14-bit register ticks LFSR
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2017-08-11 14:57:08 +00:00
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bool length_enabled; // NR44
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2019-05-15 10:39:08 +00:00
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2017-08-12 16:50:39 +00:00
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uint8_t alignment; // If (NR43 & 7) != 0, samples are aligned to 512KHz clock instead of
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// 1MHz. This variable keeps track of the alignment.
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2021-11-06 23:10:58 +00:00
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bool current_lfsr_sample;
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int8_t delta;
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bool countdown_reloaded;
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uint8_t dmg_delayed_start;
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GB_envelope_clock_t envelope_clock;
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2017-08-11 14:57:08 +00:00
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} noise_channel;
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2019-05-15 10:39:08 +00:00
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2021-11-06 23:10:58 +00:00
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enum {
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GB_SKIP_DIV_EVENT_INACTIVE,
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GB_SKIP_DIV_EVENT_SKIPPED,
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GB_SKIP_DIV_EVENT_SKIP,
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} skip_div_event:8;
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2020-05-09 21:37:52 +00:00
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uint8_t pcm_mask[2]; // For CGB-0 to CGB-C PCM read glitch
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2016-03-30 20:07:55 +00:00
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} GB_apu_t;
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2017-08-15 18:14:55 +00:00
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typedef enum {
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GB_HIGHPASS_OFF, // Do not apply any filter, keep DC offset
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GB_HIGHPASS_ACCURATE, // Apply a highpass filter similar to the one used on hardware
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GB_HIGHPASS_REMOVE_DC_OFFSET, // Remove DC Offset without affecting the waveform
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2017-12-23 19:11:44 +00:00
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GB_HIGHPASS_MAX
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2017-08-15 18:14:55 +00:00
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} GB_highpass_mode_t;
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2017-07-21 20:06:02 +00:00
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typedef struct {
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unsigned sample_rate;
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2019-05-15 10:39:08 +00:00
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2021-12-26 13:20:46 +00:00
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unsigned sample_cycles; // Counts by sample_rate until it reaches the clock frequency
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2019-05-15 10:39:08 +00:00
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2017-07-21 20:06:02 +00:00
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// Samples are NOT normalized to MAX_CH_AMP * 4 at this stage!
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unsigned cycles_since_render;
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unsigned last_update[GB_N_CHANNELS];
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GB_sample_t current_sample[GB_N_CHANNELS];
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GB_sample_t summed_samples[GB_N_CHANNELS];
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2018-02-16 16:01:50 +00:00
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double dac_discharge[GB_N_CHANNELS];
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2019-05-15 10:39:08 +00:00
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2017-08-15 18:14:55 +00:00
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GB_highpass_mode_t highpass_mode;
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double highpass_rate;
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GB_double_sample_t highpass_diff;
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2019-06-15 20:22:27 +00:00
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GB_sample_callback_t sample_callback;
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2019-10-08 12:10:24 +00:00
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2020-12-30 22:06:36 +00:00
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double interference_volume;
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double interference_highpass;
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2017-07-21 20:06:02 +00:00
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} GB_apu_output_t;
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2019-06-15 20:22:27 +00:00
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void GB_set_sample_rate(GB_gameboy_t *gb, unsigned sample_rate);
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2019-11-03 20:02:33 +00:00
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void GB_set_sample_rate_by_clocks(GB_gameboy_t *gb, double cycles_per_sample); /* Cycles are in 8MHz units */
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2017-08-15 18:14:55 +00:00
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void GB_set_highpass_filter_mode(GB_gameboy_t *gb, GB_highpass_mode_t mode);
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2020-12-30 22:06:36 +00:00
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void GB_set_interference_volume(GB_gameboy_t *gb, double volume);
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2019-06-15 20:22:27 +00:00
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void GB_apu_set_sample_callback(GB_gameboy_t *gb, GB_sample_callback_t callback);
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2020-12-30 22:06:36 +00:00
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2017-04-17 17:16:17 +00:00
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#ifdef GB_INTERNAL
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2021-11-07 12:13:52 +00:00
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internal bool GB_apu_is_DAC_enabled(GB_gameboy_t *gb, unsigned index);
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internal void GB_apu_write(GB_gameboy_t *gb, uint8_t reg, uint8_t value);
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internal uint8_t GB_apu_read(GB_gameboy_t *gb, uint8_t reg);
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internal void GB_apu_div_event(GB_gameboy_t *gb);
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internal void GB_apu_div_secondary_event(GB_gameboy_t *gb);
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internal void GB_apu_init(GB_gameboy_t *gb);
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internal void GB_apu_run(GB_gameboy_t *gb);
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2017-04-17 17:16:17 +00:00
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#endif
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2016-03-30 20:07:55 +00:00
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#endif /* apu_h */
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