radius
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3dffa3a0ca
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fix gbc
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2017-10-09 11:36:23 -05:00 |
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radius
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65e6e5f30b
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use GB_run_frame
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2017-10-09 11:36:23 -05:00 |
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twinaphex
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33a9c54842
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Correct memset lines
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2017-10-09 11:36:23 -05:00 |
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twinaphex
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d433cdf260
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Add baked-in generated BIOS files
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2017-10-09 11:36:23 -05:00 |
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Not6
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3f86d898a3
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some others input
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2017-10-09 11:36:23 -05:00 |
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Not6
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009a66d723
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basic libretro port
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2017-10-09 11:36:23 -05:00 |
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Lior Halphon
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c1f27d7b27
|
Spacing
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2017-10-02 22:59:03 +03:00 |
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Lior Halphon
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d9b0576351
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Emulation of NRX2-write glitches. Fixes Prehistorik Man audio.
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2017-10-02 22:56:24 +03:00 |
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Lior Halphon
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78446f0ed4
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Fixed several memory leaks (mostly in Cocoa port debugging utils)
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2017-09-27 22:09:26 +03:00 |
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Lior Halphon
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7a41a9b417
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Refined OAM interrupt timing. Fixes Pinball Deluxe in DMG mode; closes #1.
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2017-09-23 21:08:05 +03:00 |
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Lior Halphon
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1804a5c8e6
|
Updated save struct version
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2017-09-23 00:25:21 +03:00 |
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Lior Halphon
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67f1566b5e
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Minor refinement to sweep
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2017-09-23 00:23:02 +03:00 |
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Lior Halphon
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e0a6edac35
|
Setting sweep period to 0 cancels pending calculate event
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2017-09-22 14:53:24 +03:00 |
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Lior Halphon
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2ffce49e16
|
Minor bugfixes related to sweeping
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2017-09-22 14:39:39 +03:00 |
|
Lior Halphon
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75db33559a
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Current sample index (Channel 1 and 2) is only reset after turning the APU off
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2017-09-22 02:25:06 +03:00 |
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Lior Halphon
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8f4cd5c412
|
Corrected behavior for channel 1 and 2 restart
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2017-09-22 02:04:29 +03:00 |
|
Lior Halphon
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882b141478
|
Fixed dmg_sound-1
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2017-09-21 18:32:21 +03:00 |
|
Lior Halphon
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2ca550273a
|
Fixed dmg_sound-5
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2017-09-21 18:18:10 +03:00 |
|
Lior Halphon
|
d3c15ef6ca
|
Fixing APU bugs, one at a time: Blargg’s dmg_sound 8.2
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2017-09-21 14:52:09 +03:00 |
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Lior Halphon
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02ac609f3c
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Merge branch 'master' into new_apu
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2017-09-20 16:16:05 +03:00 |
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Lior Halphon
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be038dc8e7
|
Refinement to the last fix
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2017-09-20 03:08:54 +03:00 |
|
Lior Halphon
|
57e7782ac4
|
Interrupt servicing is now more accurate. Fixes mooneye-gb’s ie_push (all models) and Pinball Deluxe (!!!) for CGB mode
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2017-09-20 02:49:45 +03:00 |
|
Lior Halphon
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09b7e2fff4
|
Fixed a bug in scx_delay’s calculation
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2017-09-11 23:56:35 +03:00 |
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Lior Halphon
|
b9bdd6c49c
|
Merge branch 'master' into new_apu
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2017-09-10 02:33:40 +03:00 |
|
Lior Halphon
|
14f267b4fa
|
Another whoops
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2017-09-09 19:31:05 +03:00 |
|
Lior Halphon
|
02841ddde6
|
Whoops
|
2017-09-09 16:55:55 +03:00 |
|
Lior Halphon
|
026baddbab
|
Implemented delayed/future interrupts for DMG hblank interrupt. Restores vblank_stat_intr-GS support.
|
2017-09-09 13:45:01 +03:00 |
|
Lior Halphon
|
1e90400916
|
Reimplemented delayed/future interrupts, currently correct only for CGB.
|
2017-09-09 13:32:12 +03:00 |
|
Lior Halphon
|
742c9e95d3
|
Updated previous timing improvements to correctly implement double speed behavior
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2017-09-08 23:46:38 +03:00 |
|
Lior Halphon
|
e5d354e896
|
Refined SCX’s effects on PPU timing
|
2017-09-08 23:02:24 +03:00 |
|
Lior Halphon
|
0f1fa3176f
|
Refinements to LCD timing (breaks vblank_stat_intr-GS for now)
|
2017-09-08 12:59:57 +03:00 |
|
Lior Halphon
|
0f643e01b7
|
Removing the delayed interrupt mechanism, research is not complete enough for implementation
|
2017-09-08 12:58:35 +03:00 |
|
Lior Halphon
|
ba0e66a5b7
|
Merge branch 'master' into new_apu
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2017-09-04 18:41:13 +03:00 |
|
Lior Halphon
|
72d26c7046
|
Fixed obscure timer behavior, fixed regression in rapid_toggle.gb.
|
2017-09-04 18:40:43 +03:00 |
|
Lior Halphon
|
9bde98dede
|
SCY latching is now correctly emulated, rendering mode timing refined.
|
2017-09-04 15:45:18 +03:00 |
|
Lior Halphon
|
a1a13c61bf
|
On CGB, the VBlank and STAT interrupts are “delayed” by one T-cycle (relative to IF) since they’re not aligned to a T-Cycle
|
2017-09-03 00:41:52 +03:00 |
|
Lior Halphon
|
0532d2a159
|
A test ROM I wrote seems to contradicts some of AntonioND’s findings regrading PPU timing in CGB mode. CGB mode now behaves like DMG mode until I figure out what caused the difference.
|
2017-09-02 23:51:02 +03:00 |
|
Lior Halphon
|
9b490396bb
|
Fixed timing when turning the LCD display on during double speed mode
|
2017-09-02 23:26:45 +03:00 |
|
Lior Halphon
|
54eb51d8db
|
Refined timer interrupt timing
|
2017-09-02 22:08:20 +03:00 |
|
Lior Halphon
|
e7d5cdbb42
|
Merge branch 'master' into new_apu
|
2017-08-20 01:37:33 +03:00 |
|
Lior Halphon
|
cbbaf2ee84
|
Refined Window behavior once more, Fixes #12 (While not breaking Donkey Kong or 007)
|
2017-08-20 01:34:12 +03:00 |
|
Lior Halphon
|
62878fdc7a
|
More accurate div-event handling
|
2017-08-15 22:27:15 +03:00 |
|
Lior Halphon
|
8d011ca4b9
|
Accuracy improvements (Sweep)
|
2017-08-15 22:05:20 +03:00 |
|
Lior Halphon
|
5d84ee250e
|
Added Cocoa GUI for the High-Pass filter selection
|
2017-08-15 21:59:53 +03:00 |
|
Lior Halphon
|
d04aaddcbd
|
Added highpass filter
|
2017-08-15 21:59:11 +03:00 |
|
Lior Halphon
|
ca59aca4a6
|
Fixed a bug where writing to NR52 affected channels 1 and 2’s duty pattern in DMG mode. Fixed NR43 being written to NR44 as well.
|
2017-08-13 20:26:35 +03:00 |
|
Lior Halphon
|
36943866e2
|
Better click prevention
|
2017-08-12 23:35:18 +03:00 |
|
Lior Halphon
|
d43daed6a6
|
Merge branch 'master' into new_apu
|
2017-08-12 21:43:09 +03:00 |
|
Lior Halphon
|
7df4e56454
|
KEY1 is only writable in CGB mode; screen should be black is LCD is on while in stop mode.
|
2017-08-12 21:42:47 +03:00 |
|
Lior Halphon
|
dba7370d6d
|
Turns out APU signal is inverted. This fixes Perfect Dark’s audio.
|
2017-08-12 20:47:55 +03:00 |
|