Commit Graph

390 Commits

Author SHA1 Message Date
ggf906
a009616726 (VITA) Fix compilation 2017-10-09 11:36:55 -05:00
twinaphex
a7db98c22e Memory needs to be uniquely named for Android 2017-10-09 11:36:55 -05:00
twinaphex
b02aeab022 We don't need stdin 2017-10-09 11:36:54 -05:00
twinaphex
5e3a24573e Bump up version 2017-10-09 11:36:54 -05:00
twinaphex
091df682cd Silence warning 2017-10-09 11:36:54 -05:00
twinaphex
09f4edda57 Comment out debugger code - add HAVE_DEBUGGER ifdef 2017-10-09 11:36:53 -05:00
twinaphex
aeea20ae9d Comment out nsleep 2017-10-09 11:36:53 -05:00
twinaphex
9f5b746e0b Fix compiler error 2017-10-09 11:36:53 -05:00
twinaphex
63b17e14af Update 2017-10-09 11:36:24 -05:00
twinaphex
fedea2cad7 Don't hook up regular audio_cb 2017-10-09 11:36:24 -05:00
radius
7d2dbe2988 no need for turbo mode in libretro 2017-10-09 11:36:24 -05:00
radius
765a072c73 this fixes fast forwarding but probably has to change to a proper fix 2017-10-09 11:36:24 -05:00
radius
3dffa3a0ca fix gbc 2017-10-09 11:36:23 -05:00
radius
65e6e5f30b use GB_run_frame 2017-10-09 11:36:23 -05:00
twinaphex
33a9c54842 Correct memset lines 2017-10-09 11:36:23 -05:00
twinaphex
d433cdf260 Add baked-in generated BIOS files 2017-10-09 11:36:23 -05:00
Not6
3f86d898a3 some others input 2017-10-09 11:36:23 -05:00
Not6
009a66d723 basic libretro port 2017-10-09 11:36:23 -05:00
Lior Halphon
c1f27d7b27 Spacing 2017-10-02 22:59:03 +03:00
Lior Halphon
d9b0576351 Emulation of NRX2-write glitches. Fixes Prehistorik Man audio. 2017-10-02 22:56:24 +03:00
Lior Halphon
78446f0ed4 Fixed several memory leaks (mostly in Cocoa port debugging utils) 2017-09-27 22:09:26 +03:00
Lior Halphon
7a41a9b417 Refined OAM interrupt timing. Fixes Pinball Deluxe in DMG mode; closes #1. 2017-09-23 21:08:05 +03:00
Lior Halphon
1804a5c8e6 Updated save struct version 2017-09-23 00:25:21 +03:00
Lior Halphon
67f1566b5e Minor refinement to sweep 2017-09-23 00:23:02 +03:00
Lior Halphon
e0a6edac35 Setting sweep period to 0 cancels pending calculate event 2017-09-22 14:53:24 +03:00
Lior Halphon
2ffce49e16 Minor bugfixes related to sweeping 2017-09-22 14:39:39 +03:00
Lior Halphon
75db33559a Current sample index (Channel 1 and 2) is only reset after turning the APU off 2017-09-22 02:25:06 +03:00
Lior Halphon
8f4cd5c412 Corrected behavior for channel 1 and 2 restart 2017-09-22 02:04:29 +03:00
Lior Halphon
882b141478 Fixed dmg_sound-1 2017-09-21 18:32:21 +03:00
Lior Halphon
2ca550273a Fixed dmg_sound-5 2017-09-21 18:18:10 +03:00
Lior Halphon
d3c15ef6ca Fixing APU bugs, one at a time: Blargg’s dmg_sound 8.2 2017-09-21 14:52:09 +03:00
Lior Halphon
02ac609f3c Merge branch 'master' into new_apu 2017-09-20 16:16:05 +03:00
Lior Halphon
be038dc8e7 Refinement to the last fix 2017-09-20 03:08:54 +03:00
Lior Halphon
57e7782ac4 Interrupt servicing is now more accurate. Fixes mooneye-gb’s ie_push (all models) and Pinball Deluxe (!!!) for CGB mode 2017-09-20 02:49:45 +03:00
Lior Halphon
09b7e2fff4 Fixed a bug in scx_delay’s calculation 2017-09-11 23:56:35 +03:00
Lior Halphon
b9bdd6c49c Merge branch 'master' into new_apu 2017-09-10 02:33:40 +03:00
Lior Halphon
14f267b4fa Another whoops 2017-09-09 19:31:05 +03:00
Lior Halphon
02841ddde6 Whoops 2017-09-09 16:55:55 +03:00
Lior Halphon
026baddbab Implemented delayed/future interrupts for DMG hblank interrupt. Restores vblank_stat_intr-GS support. 2017-09-09 13:45:01 +03:00
Lior Halphon
1e90400916 Reimplemented delayed/future interrupts, currently correct only for CGB. 2017-09-09 13:32:12 +03:00
Lior Halphon
742c9e95d3 Updated previous timing improvements to correctly implement double speed behavior 2017-09-08 23:46:38 +03:00
Lior Halphon
e5d354e896 Refined SCX’s effects on PPU timing 2017-09-08 23:02:24 +03:00
Lior Halphon
0f1fa3176f Refinements to LCD timing (breaks vblank_stat_intr-GS for now) 2017-09-08 12:59:57 +03:00
Lior Halphon
0f643e01b7 Removing the delayed interrupt mechanism, research is not complete enough for implementation 2017-09-08 12:58:35 +03:00
Lior Halphon
ba0e66a5b7 Merge branch 'master' into new_apu 2017-09-04 18:41:13 +03:00
Lior Halphon
72d26c7046 Fixed obscure timer behavior, fixed regression in rapid_toggle.gb. 2017-09-04 18:40:43 +03:00
Lior Halphon
9bde98dede SCY latching is now correctly emulated, rendering mode timing refined. 2017-09-04 15:45:18 +03:00
Lior Halphon
a1a13c61bf On CGB, the VBlank and STAT interrupts are “delayed” by one T-cycle (relative to IF) since they’re not aligned to a T-Cycle 2017-09-03 00:41:52 +03:00
Lior Halphon
0532d2a159 A test ROM I wrote seems to contradicts some of AntonioND’s findings regrading PPU timing in CGB mode. CGB mode now behaves like DMG mode until I figure out what caused the difference. 2017-09-02 23:51:02 +03:00
Lior Halphon
9b490396bb Fixed timing when turning the LCD display on during double speed mode 2017-09-02 23:26:45 +03:00