Lior Halphon
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769aac93c0
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Lazy APU, extra ~17% speed up
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2021-12-29 00:48:44 +02:00 |
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Lior Halphon
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c53d99dbc4
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Abolished slow double use
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2021-12-26 15:20:46 +02:00 |
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Lior Halphon
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f866441481
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Improved emulation of channel 3 wave RAM read glitch
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2021-12-19 19:27:40 +02:00 |
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Lior Halphon
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02f55d12d3
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Maybe one day GCC will stop being shit at handling __attribute__s
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2021-11-07 14:13:52 +02:00 |
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Lior Halphon
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18e7a3f4fa
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Cleanup, better symbol handling, improves LTO
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2021-11-07 13:39:18 +02:00 |
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Lior Halphon
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fbf1bb7f98
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Save state compatibility breaking cleanup
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2021-11-07 12:56:46 +02:00 |
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Lior Halphon
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94776fcf8c
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Better (But imperfect) emulation of the wave RAM address bug glitch
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2021-10-19 01:53:24 +03:00 |
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Lior Halphon
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de16ab5d08
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Why was this under APU
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2021-10-17 20:05:49 +03:00 |
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Lior Halphon
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7ef198ec50
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More accurate channel 3 restarts
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2021-10-17 02:06:33 +03:00 |
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Lior Halphon
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4c05ebcea6
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Redo the volume envelope with better timings, locking emulation and zombie mode edge cases. Fixes #344
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2021-02-25 15:43:38 +02:00 |
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Lior Halphon
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393269ae1f
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Emulate volume envelope locking
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2021-02-22 13:48:56 +02:00 |
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Lior Halphon
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c0582fd994
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More accurate emulation of NR10 writes
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2021-01-09 00:31:16 +02:00 |
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Lior Halphon
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b54a72d9b9
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Fixing a bug where where zero-shift sweep wouldn't tick
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2021-01-02 14:56:45 +02:00 |
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Lior Halphon
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5c854dbdca
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Interference emulation
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2020-12-31 00:07:04 +02:00 |
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Lior Halphon
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4f408eae7c
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Whoops
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2020-12-12 18:13:55 +02:00 |
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Lior Halphon
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7de6194e28
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Redo channel 4's timing accurately, emulate NR43 write quirks
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2020-12-12 16:02:25 +02:00 |
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Lior Halphon
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1baa0446a9
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More sweep improvements
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2020-12-01 22:37:13 +02:00 |
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Lior Halphon
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74cf452a48
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Further accuracy improvements to sweep; passes Blargg's APU tests again, this time for real
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2020-12-01 14:17:35 +02:00 |
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Lior Halphon
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0485124076
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Redo channel 1 sweep based on DMG schematics; emulates two newly discovered behaviors and also fixes #309
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2020-11-28 19:31:25 +02:00 |
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Lior Halphon
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3cba3e8e27
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Emulate CGB-C PCM read glitch, fix a potential noise volume envelope bug
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2020-05-10 00:37:52 +03:00 |
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Jakub Kądziołka
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67d5a53503
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Spell "length" properly
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2020-02-27 18:11:10 +01:00 |
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Lior Halphon
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103caa56e1
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Allow displaying borders outside of SGB emulation, including borrowing SGB border. Allow not displaying SGB borders. (Todo: libretro support)
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2020-02-08 13:28:46 +02:00 |
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Lior Halphon
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b806ae4e82
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Fix #228
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2020-02-01 23:36:16 +02:00 |
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Lior Halphon
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143e1f88a8
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There’s not reason it must be an integer
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2019-11-03 22:02:33 +02:00 |
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Lior Halphon
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dee29c118c
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Added GB_set_sample_rate_by_clocks API, split SGB_NO_SFC into PAL and NTSC; now they report the correct clock rate.
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2019-10-08 15:10:24 +03:00 |
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Lior Halphon
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e268efefef
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Redesign and reimplement the audio API, let the frontends handle more stuff. Probably affects #161
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2019-06-15 23:22:27 +03:00 |
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Lior Halphon
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9d8adbb581
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This is not correct, this bug only affects the PCM registers and not actual output. Currently not emulated at all.
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2019-06-07 18:37:19 +03:00 |
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Lior Halphon
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85c43fa81f
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Fixed Channel 3’s first sample behavior, update analog characteristic to more realistic values. Fixes #177
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2019-05-25 19:12:09 +03:00 |
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ISSOtm
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40f83c8f25
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Add APU-related debugger commands
This change includes making one of the APU functions public
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2019-05-15 12:45:51 +02:00 |
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Lior Halphon
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4051f190a5
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Cache cycles_per_sample to avoid FP arithmetic
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2019-01-01 00:42:40 +02:00 |
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Lior Halphon
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94136f5741
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Adjust DAC attributes to fix LADX’s crackling audio (Fixes #125) while keeping Cannon Fodder’s buzzing reasonable (Proper audio measurements still required)
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2018-11-10 19:14:18 +02:00 |
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Lior Halphon
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64922fff4b
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Fixed a bug where channels 1 and 2 would start playing earlier than they should have if NRx4 was written to twice. Fixes #86.
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2018-10-29 00:44:43 +02:00 |
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Lior Halphon
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3035f43428
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Emulation of DAC charging, Fixes #46, #85, #88 and #89
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2018-10-19 23:53:01 +03:00 |
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Lior Halphon
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324201f336
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Correct emulation of switching the DACs on and off. Fixes #100 and #87
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2018-10-17 20:35:29 +03:00 |
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Lior Halphon
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dc5cb71c22
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Emulate CGB-C’s quirky LFSR function
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2018-07-04 21:55:12 +03:00 |
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Lior Halphon
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f64da1864f
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APU glitch: When turning the APU on while DIV's bit 4 (or 5 in double speed mode), the first DIV/APU event is skipped.
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2018-06-09 15:11:20 +03:00 |
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Lior Halphon
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80c92daacd
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Include cleanup (#73)
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2018-05-27 19:30:23 +03:00 |
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Lior Halphon
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9802ca41dd
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Components not affected by CGB’s double speed mode now operate in 8MHz mode to theoretically make advance_cycles(gb, 1) safe.
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2018-02-20 21:17:12 +02:00 |
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Lior Halphon
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f79af39ea2
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More accurate emulation of the APU’s analog characteristics
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2018-02-16 18:01:50 +02:00 |
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Lior Halphon
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fc35111ae7
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Corrected the emulated DAC’s range
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2018-02-16 01:26:37 +02:00 |
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Lior Halphon
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81f808e184
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Refinements for the Wii U port
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2018-02-10 15:02:22 +02:00 |
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radius
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217e9787bd
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change MAX_CH_AMP on WiiU
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2018-02-07 15:28:30 -05:00 |
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Lior Halphon
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a1af4c59ca
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Fixed NR51 volume levels (They’re 1-8, not 0-7)
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2018-01-06 11:58:49 +02:00 |
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Lior Halphon
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dc59fdf40e
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Highpass filter in SDL
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2017-12-23 22:11:53 +02:00 |
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Lior Halphon
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8f4cd5c412
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Corrected behavior for channel 1 and 2 restart
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2017-09-22 02:04:29 +03:00 |
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Lior Halphon
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2ca550273a
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Fixed dmg_sound-5
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2017-09-21 18:18:10 +03:00 |
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Lior Halphon
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8d011ca4b9
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Accuracy improvements (Sweep)
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2017-08-15 22:05:20 +03:00 |
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Lior Halphon
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d04aaddcbd
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Added highpass filter
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2017-08-15 21:59:11 +03:00 |
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Lior Halphon
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4b8be255ce
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Fixed some channel 4 delays, documented a not currently emulated timing quirk.
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2017-08-12 19:50:39 +03:00 |
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Lior Halphon
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066efab985
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In DMG mode, the length registers are not affected by turning the APU on and off. Why? Why not!
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2017-08-11 22:23:03 +03:00 |