Lior Halphon
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75db33559a
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Current sample index (Channel 1 and 2) is only reset after turning the APU off
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2017-09-22 02:25:06 +03:00 |
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Lior Halphon
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8f4cd5c412
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Corrected behavior for channel 1 and 2 restart
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2017-09-22 02:04:29 +03:00 |
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Lior Halphon
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882b141478
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Fixed dmg_sound-1
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2017-09-21 18:32:21 +03:00 |
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Lior Halphon
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2ca550273a
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Fixed dmg_sound-5
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2017-09-21 18:18:10 +03:00 |
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Lior Halphon
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d3c15ef6ca
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Fixing APU bugs, one at a time: Blargg’s dmg_sound 8.2
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2017-09-21 14:52:09 +03:00 |
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Lior Halphon
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02ac609f3c
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Merge branch 'master' into new_apu
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2017-09-20 16:16:05 +03:00 |
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Lior Halphon
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be038dc8e7
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Refinement to the last fix
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2017-09-20 03:08:54 +03:00 |
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Lior Halphon
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57e7782ac4
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Interrupt servicing is now more accurate. Fixes mooneye-gb’s ie_push (all models) and Pinball Deluxe (!!!) for CGB mode
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2017-09-20 02:49:45 +03:00 |
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Lior Halphon
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09b7e2fff4
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Fixed a bug in scx_delay’s calculation
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2017-09-11 23:56:35 +03:00 |
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Lior Halphon
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b9bdd6c49c
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Merge branch 'master' into new_apu
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2017-09-10 02:33:40 +03:00 |
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Lior Halphon
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14f267b4fa
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Another whoops
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2017-09-09 19:31:05 +03:00 |
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Lior Halphon
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02841ddde6
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Whoops
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2017-09-09 16:55:55 +03:00 |
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Lior Halphon
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026baddbab
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Implemented delayed/future interrupts for DMG hblank interrupt. Restores vblank_stat_intr-GS support.
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2017-09-09 13:45:01 +03:00 |
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Lior Halphon
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1e90400916
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Reimplemented delayed/future interrupts, currently correct only for CGB.
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2017-09-09 13:32:12 +03:00 |
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Lior Halphon
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742c9e95d3
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Updated previous timing improvements to correctly implement double speed behavior
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2017-09-08 23:46:38 +03:00 |
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Lior Halphon
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e5d354e896
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Refined SCX’s effects on PPU timing
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2017-09-08 23:02:24 +03:00 |
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Lior Halphon
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0f1fa3176f
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Refinements to LCD timing (breaks vblank_stat_intr-GS for now)
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2017-09-08 12:59:57 +03:00 |
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Lior Halphon
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0f643e01b7
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Removing the delayed interrupt mechanism, research is not complete enough for implementation
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2017-09-08 12:58:35 +03:00 |
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Lior Halphon
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ba0e66a5b7
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Merge branch 'master' into new_apu
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2017-09-04 18:41:13 +03:00 |
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Lior Halphon
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72d26c7046
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Fixed obscure timer behavior, fixed regression in rapid_toggle.gb.
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2017-09-04 18:40:43 +03:00 |
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Lior Halphon
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9bde98dede
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SCY latching is now correctly emulated, rendering mode timing refined.
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2017-09-04 15:45:18 +03:00 |
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Lior Halphon
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a1a13c61bf
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On CGB, the VBlank and STAT interrupts are “delayed” by one T-cycle (relative to IF) since they’re not aligned to a T-Cycle
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2017-09-03 00:41:52 +03:00 |
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Lior Halphon
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0532d2a159
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A test ROM I wrote seems to contradicts some of AntonioND’s findings regrading PPU timing in CGB mode. CGB mode now behaves like DMG mode until I figure out what caused the difference.
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2017-09-02 23:51:02 +03:00 |
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Lior Halphon
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9b490396bb
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Fixed timing when turning the LCD display on during double speed mode
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2017-09-02 23:26:45 +03:00 |
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Lior Halphon
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54eb51d8db
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Refined timer interrupt timing
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2017-09-02 22:08:20 +03:00 |
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Lior Halphon
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e7d5cdbb42
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Merge branch 'master' into new_apu
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2017-08-20 01:37:33 +03:00 |
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Lior Halphon
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cbbaf2ee84
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Refined Window behavior once more, Fixes #12 (While not breaking Donkey Kong or 007)
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2017-08-20 01:34:12 +03:00 |
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Lior Halphon
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62878fdc7a
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More accurate div-event handling
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2017-08-15 22:27:15 +03:00 |
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Lior Halphon
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8d011ca4b9
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Accuracy improvements (Sweep)
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2017-08-15 22:05:20 +03:00 |
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Lior Halphon
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d04aaddcbd
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Added highpass filter
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2017-08-15 21:59:11 +03:00 |
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Lior Halphon
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ca59aca4a6
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Fixed a bug where writing to NR52 affected channels 1 and 2’s duty pattern in DMG mode. Fixed NR43 being written to NR44 as well.
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2017-08-13 20:26:35 +03:00 |
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Lior Halphon
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36943866e2
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Better click prevention
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2017-08-12 23:35:18 +03:00 |
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Lior Halphon
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d43daed6a6
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Merge branch 'master' into new_apu
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2017-08-12 21:43:09 +03:00 |
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Lior Halphon
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7df4e56454
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KEY1 is only writable in CGB mode; screen should be black is LCD is on while in stop mode.
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2017-08-12 21:42:47 +03:00 |
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Lior Halphon
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dba7370d6d
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Turns out APU signal is inverted. This fixes Perfect Dark’s audio.
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2017-08-12 20:47:55 +03:00 |
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Lior Halphon
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688991f57f
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The volume envelopes and length controls are handled in different phases of the div-divider
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2017-08-12 20:17:20 +03:00 |
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Lior Halphon
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4b8be255ce
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Fixed some channel 4 delays, documented a not currently emulated timing quirk.
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2017-08-12 19:50:39 +03:00 |
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Lior Halphon
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066efab985
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In DMG mode, the length registers are not affected by turning the APU on and off. Why? Why not!
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2017-08-11 22:23:03 +03:00 |
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Lior Halphon
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0e22ad8eb1
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Noise channel support
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2017-08-11 17:57:08 +03:00 |
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Lior Halphon
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1a8bcd314d
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Accuracy improvements to sweeping (Still not complete though, more research needed)
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2017-08-10 19:42:23 +03:00 |
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Lior Halphon
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ab5611119a
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Accuracy improvements, especially to the length control
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2017-08-02 21:14:23 +03:00 |
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Lior Halphon
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d65c2247e5
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Added channel 1 and 2, fixed accuracy issues with channel 3
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2017-07-27 23:11:33 +03:00 |
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Lior Halphon
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2936f7fa57
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Fixed channel 3 counter behavior, verified with new tests. The DIV register ticks the APU at 512Hz.
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2017-07-22 19:51:11 +03:00 |
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Lior Halphon
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a19ee1e5e0
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2MHz audio downscaling support. Implemented NR50 and NR51.
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2017-07-21 23:17:48 +03:00 |
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Lior Halphon
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baccf336d7
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Complete rewrite of the APU. Channel 3 is complete and passes all the relevant tests from blargg’s suite, as well as PCM34-based tests. Actual sound output is basic and limited, though.
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2017-07-21 19:06:55 +03:00 |
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nattthebear
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eb7492c6c6
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Fix undefined behavior (sequence point modification). GCC 4.6.4 compiles the code incorrectly without this fix.
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2017-07-16 21:08:07 -04:00 |
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Lior Halphon
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c4ccbd5cce
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Improved serial interrupt timing, fixes boot_sclk_align.
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2017-06-23 17:58:04 +03:00 |
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Lior Halphon
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c59272d46d
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Misc minor fixes, fixes several Mooneye-GB tests
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2017-06-21 20:39:23 +03:00 |
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Lior Halphon
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efbc385417
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Forgot to amend the last commit, it was broken.
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2017-06-21 01:07:11 +03:00 |
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Lior Halphon
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aefca34b39
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Improved MBC1 emulation. Fixed incorrect error messages.
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2017-06-19 19:46:09 +03:00 |